公开(公告)号：US20180011961A1

公开(公告)日：2018-01-11

申请号：US15711390

申请日：2017-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangok Jeong

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.

公开(公告)号：US20240213133A1

公开(公告)日：2024-06-27

申请号：US18208415

申请日：2023-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun PARK ,  Gyuho Kang ,  Seong-Hoon Bae ,  Sang-Hyuck Oh ,  Kwangok Jeong ,  Ju-Il Choi

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/10674

Abstract: A redistribution substrate includes first and second insulating layers; a wiring layer, and a metal layer. The wiring pattern includes a via portion penetrating the first insulating layer and a pad portion on the via portion, the pad portion extending onto an upper surface of the first insulating layer. The metal layer covers an upper surface of the wiring pattern. The second insulating layer is provided on the first insulating layer and covers the pad portion and the metal layer. The wiring pattern includes a first metal. The metal layer includes the first metal and a second metal. The metal layer includes a first portion vertically overlapping the pad portion, and a second portion surrounding the first portion, and a concentration of the first metal in the first portion of the metal layer is greater than a concentration of the first metal in the second portion of the metal layer.

公开(公告)号：US20240055342A1

公开(公告)日：2024-02-15

申请号：US18316482

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangok Jeong

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L24/16

Abstract: An electronic package includes a redistribution wiring layer having redistribution wiring with a redistribution pad, and a bonding pad on the redistribution pad of the redistribution wiring. The bonding pad includes first, second, and third plating patterns. The first plating pattern is on the redistribution pad, and the first plating pattern includes a first material. Moreover, the first plating pattern has an inclined sidewall so that a diameter of the first plating patter decreases with increasing distance from the redistribution pad so that a first diameter of the first plating pattern adjacent the redistribution pad is greater than a second diameter of the first plating pattern spaced apart from the redistribution pad. The second plating pattern is on the first plating pattern, and the second plating pattern includes a second material different than the first material. The third plating pattern is on the second plating pattern, and the third plating pattern includes a third material different than the second material. Moreover, the second and third plating patterns have a same diameter that is no greater than the second diameter of the first plating pattern.

公开(公告)号：US09887210B2

公开(公告)日：2018-02-06

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC: H01L21/76 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/8238 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20250062213A1

公开(公告)日：2025-02-20

申请号：US18731988

申请日：2024-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho Kang ,  Hyungjun Park ,  Kwangok Jeong ,  Juil Choi ,  Taeoh Ha ,  Hongseo Heo

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a lower redistribution wiring layer that includes first redistribution wirings, a protective layer that defines openings, and bonding pads that are on the protective layer and are electrically connected to the first redistribution wirings through the openings; conductive bumps that are on first bonding pads of the bonding pads; and a semiconductor chip on the first bonding pads, where each of the bonding pads includes: a conductive pillar in a respective opening of the openings of the protective layer, where the conductive pillar includes a first diameter; and a pad pattern that is on the protective layer and an upper surface of the conductive pillar, where the pad pattern includes a second diameter that is greater than the first diameter.

公开(公告)号：US20240162127A1

公开(公告)日：2024-05-16

申请号：US18216157

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghyuck Oh ,  Seonghoon Bae ,  Kwangok Jeong

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package according to an example embodiment of the present disclosure comprises: a lower redistribution structure including an insulating layer, a connection pad disposed on an upper surface of the insulating layer, and an upper pad; a semiconductor chip mounted on the lower redistribution structure and connected to the upper pad; a conductive post disposed on the connection pad; at least one dummy post disposed on the lower redistribution structure; and an upper redistribution structure disposed on the semiconductor chip and connected to the conductive post, and a height of the at least one dummy post is smaller than a height of the conductive post.

公开(公告)号：US10050058B2

公开(公告)日：2018-08-14

申请号：US15282206

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong Song ,  Ha-Young Kim ,  Jung-Ho Do ,  Sanghoon Baek ,  Jinyoung Lim ,  Kwangok Jeong

IPC: H01L21/8238 ,  H01L27/118 ,  G06F17/50 ,  G03F1/36 ,  H01L21/66 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20180226303A1

公开(公告)日：2018-08-09

申请号：US15856444

申请日：2017-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYOSIG WON ,  Sang-Kyu Oh ,  Sungmin Oh ,  Kwangok Jeong

IPC: H01L21/66 ,  H01L21/8238 ,  G01N23/2251 ,  G01R31/26

CPC classification number: H01L22/10 ,  G01N23/2251 ,  G01R31/2644 ,  G01R31/2856 ,  G01R31/307 ,  H01L21/8238 ,  H01L22/12 ,  H01L22/30 ,  H01L27/1104

Abstract: A method of manufacturing a semiconductor device includes forming transistors in a cell region of a test wafer, forming a first test pattern on a first test cell in the cell region, the first test pattern being electrically connected to the transistors, and scanning the first test pattern using an electron beam. Forming the transistors in the cell region includes patterning an upper portion of the test wafer to form active patterns, forming source/drain regions on the active patterns, forming gate electrodes extending across the active patterns, forming active contacts coupled to the source/drain regions, and forming gate contacts coupled to the gate electrodes.

公开(公告)号：US10002223B2

公开(公告)日：2018-06-19

申请号：US15711390

申请日：2017-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangok Jeong

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.