公开(公告)号：US20190130958A1

公开(公告)日：2019-05-02

申请号：US16005880

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Kee-Won Kwon ,  Ji-Su Min ,  Rak-Joo Sung ,  Sung-gi Ahn

IPC: G11C11/22 ,  G11C5/06 ,  G11C7/12

CPC classification number: G11C11/2293 ,  G11C5/063 ,  G11C7/12 ,  G11C15/04 ,  G11C15/043

Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

公开(公告)号：US09659641B2

公开(公告)日：2017-05-23

申请号：US14660530

申请日：2015-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Kyung Kim ,  Kee-Won Kwon

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2013/0054

Abstract: A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

公开(公告)号：US09654118B2

公开(公告)日：2017-05-16

申请号：US15179202

申请日：2016-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan Bae ,  Kee-Won Kwon ,  Kyungho Kim ,  Jung Hoon Chun ,  Youngsoo Sohn ,  Seok Kim

IPC: H03L7/085 ,  H03D13/00 ,  H03L7/089 ,  H03L7/087 ,  H03L7/081 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

公开(公告)号：US10482962B2

公开(公告)日：2019-11-19

申请号：US15979669

申请日：2018-05-15

Applicant: Samsung Electronics Co., Ltd. ,  Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

Inventor： Cheol Kim ,  Hyun-Suk Kang ,  Kee-Won Kwon ,  Rak-Joo Sung ,  Sung-Gi Ahn

IPC: G11C15/04 ,  G11C15/00 ,  G11C13/00

Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

公开(公告)号：US10395719B2

公开(公告)日：2019-08-27

申请号：US16005880

申请日：2018-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheol Kim ,  Kee-Won Kwon ,  Ji-Su Min ,  Rak-Joo Sung ,  Sung-gi Ahn

IPC: G11C11/22 ,  G11C7/12 ,  G11C5/06 ,  G11C15/04

Abstract: A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.