公开(公告)号：US20160293445A1

公开(公告)日：2016-10-06

申请号：US15066492

申请日：2016-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Woo HAN ,  Junho YOON ,  Kyohyeok KIM ,  Dongchan KIM ,  Sungyeon KIM ,  Jaehong PARK ,  Jinyoung PARK ,  KyungYub JEON

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

Abstract translation: 公开了制造半导体器件的方法。 该方法可以包括在衬底上形成目标层，在目标层上形成掩模图案，执行蚀刻目标层并形成第一子沟槽的第一工艺，以及执行第二工艺以进一步蚀刻目标层和 形成第二子沟槽。 第一和第二侧壁图案可分别形成在掩模图案的侧壁上，以分别在第一和第二工艺中用作蚀刻掩模。 第一和第二侧壁图案的外侧壁可以形成为相对于基板的顶表面具有不同的角度。

公开(公告)号：US20250167012A1

公开(公告)日：2025-05-22

申请号：US18794556

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihoon JEONG ,  Junho YOON ,  Young-Hoo KIM ,  Taeheon KIM ,  Woogwan SHIM ,  Jongwon LEE ,  Junho LEE ,  Jiwoong JUNG

IPC: H01L21/67 ,  B08B3/04 ,  B08B3/08 ,  H01L21/02

Abstract: A substrate processing apparatus includes a stage configured to support a substrate, a rotation driving portion configured to rotate the stage around a first axis extending in a vertical direction, a first nozzle arm disposed on the stage and configured to rotate around a second axis parallel to the first axis, and a second nozzle arm disposed on the stage and configured to rotate around a third axis parallel to the second axis. The first nozzle arm includes a first nozzle supporting member extended parallel to the stage, a first connection member coupled to an end of the first nozzle supporting member, the first connection member having a stepwise shape, and a first nozzle coupled to the first connection member and configured to spray a fluidic material.

公开(公告)号：US20250120194A1

公开(公告)日：2025-04-10

申请号：US18901417

申请日：2024-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Junho YOON ,  Gyeonghee LEE ,  Dongwoon LEE ,  Jaehyeok LEE

IPC: H01L27/146

Abstract: An image sensor includes a substrate including a first region and a second region. A photodiode is in the first region of the substrate. A color filter array layer is on the first region of the substrate. The color filter array layer includes color filters. A pad structure extends through an upper portion of the second region of the substrate and protrudes upwardly over an upper surface of the substrate in a vertical direction substantially perpendicular to the upper surface of the substrate. A dummy structure is spaced apart from the pad structure on the second region of the substrate.

公开(公告)号：US20200373124A1

公开(公告)日：2020-11-26

申请号：US16706773

申请日：2019-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

IPC: H01J37/32

Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.

公开(公告)号：US20250046747A1

公开(公告)日：2025-02-06

申请号：US18417810

申请日：2024-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun KWEON ,  Wooju KIM ,  Kangil YUN ,  Junho YOON ,  Dayoung CHO ,  Jinwook HONG

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate and including a first chip pad and a first upper insulating layer on sidewalls of the first chip pad, a first bonding wire on a top surface of the first chip pad and connected to the first chip pad, and a second semiconductor chip on a top surface of the first semiconductor chip and spaced apart from the first chip pad, wherein the second semiconductor chip includes a second semiconductor die and a second lower insulating layer on a bottom surface of the second semiconductor die, wherein the second lower insulating layer may be directly bonded to the first upper insulating layer by a chemical bond between the first upper insulating layer and the second lower insulating layer.

公开(公告)号：US20240038493A1

公开(公告)日：2024-02-01

申请号：US18380144

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Yonghwan KIM ,  Sangwuk PARK ,  Chanhoon PARK ,  Hyuk KIM ,  Edward SUNG

IPC: H01J37/32

CPC classification number: H01J37/32082 ,  H01L21/31144

Abstract: A semiconductor processing apparatus includes an upper electrode and a substrate on a lower electrode disposed inside the process chamber, a first power generator configured to provide a low-frequency signal to the lower electrode, wherein the low-frequency signal varies between a reference voltage and a first voltage at intervals of a first cycle, a second power generator configured to provide a high-frequency signal to the lower electrode, wherein the high-frequency signal has a sinusoidal waveform that oscillates at intervals of a second cycle shorter than the first cycle, and a direct-current (DC) power generator configured to provide a DC bias to the upper electrode. The high-frequency signal is turned off during at least part of a duration for which the low-frequency signal has the first voltage, and the high-frequency signal is turned on and turned off at intervals of a third cycle different from the first and second cycles.

公开(公告)号：US20160314981A1

公开(公告)日：2016-10-27

申请号：US15084479

申请日：2016-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  KyungYub JEON ,  Kyohyeok KIM ,  Jaehong PARK ,  Je-Woo HAN

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/28044 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1085

Abstract: A method for forming a vertical pattern includes forming a tungsten layer on a lower layer and performing a cyclic process including an etch process and an oxidation process on the tungsten layer to form a vertical pattern. Performing the cyclic process includes oxidizing the tungsten layer by an oxidation process using oxygen plasma to form a tungsten oxide layer and selectively etching the tungsten oxide layer by an etch process using a chlorine-based gas.

Abstract translation: 用于形成垂直图案的方法包括在下层上形成钨层，并在钨层上执行包括蚀刻工艺和氧化工艺的循环过程以形成垂直图案。 执行循环过程包括通过使用氧等离子体的氧化工艺氧化钨层以形成氧化钨层，并通过使用氯基气体的蚀刻工艺选择性地蚀刻氧化钨层。

公开(公告)号：US20250125160A1

公开(公告)日：2025-04-17

申请号：US18908049

申请日：2024-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeheon KIM ,  Junho LEE ,  Younghoo KIM ,  Junho YOON ,  Jongwon LEE ,  Jiwoong JUNG ,  Jihoon JEONG

IPC: H01L21/67

Abstract: A substrate processing apparatus includes a process chamber including a processing space, a substrate support configured to support a substrate in the process chamber, a fluid supply tube arranged in a lower portion of the process chamber, and a fluid supply device configured to supply a supercritical fluid to the processing space through the fluid supply tube, wherein the substrate support includes a plate structure, which is arranged in a central region of the substrate support, and on which the substrate is settled, a turbulence reduction body having a ring shape and joined to an outer portion of the plate structure, and a turbulence reduction wing joined to an outer portion of the turbulence reduction body and tilted at a certain angle toward the lower portion of the process chamber.

公开(公告)号：US20230260845A1

公开(公告)日：2023-08-17

申请号：US17896578

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  YeongBeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Junho YOON

IPC: H01L21/8234 ,  H01L23/00

CPC classification number: H01L21/823437 ,  H01L21/823475 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16145

Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.

公开(公告)号：US20220208610A1

公开(公告)日：2022-06-30

申请号：US17699570

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  Jungchul LEE ,  Byungmoon BAE ,  Junggeun SHIN ,  Hyunsu SIM

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.