公开(公告)号：US20160314981A1

公开(公告)日：2016-10-27

申请号：US15084479

申请日：2016-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho YOON ,  KyungYub JEON ,  Kyohyeok KIM ,  Jaehong PARK ,  Je-Woo HAN

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/3081 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/28044 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1085

Abstract: A method for forming a vertical pattern includes forming a tungsten layer on a lower layer and performing a cyclic process including an etch process and an oxidation process on the tungsten layer to form a vertical pattern. Performing the cyclic process includes oxidizing the tungsten layer by an oxidation process using oxygen plasma to form a tungsten oxide layer and selectively etching the tungsten oxide layer by an etch process using a chlorine-based gas.

Abstract translation: 用于形成垂直图案的方法包括在下层上形成钨层，并在钨层上执行包括蚀刻工艺和氧化工艺的循环过程以形成垂直图案。 执行循环过程包括通过使用氧等离子体的氧化工艺氧化钨层以形成氧化钨层，并通过使用氯基气体的蚀刻工艺选择性地蚀刻氧化钨层。

公开(公告)号：US20160293445A1

公开(公告)日：2016-10-06

申请号：US15066492

申请日：2016-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Woo HAN ,  Junho YOON ,  Kyohyeok KIM ,  Dongchan KIM ,  Sungyeon KIM ,  Jaehong PARK ,  Jinyoung PARK ,  KyungYub JEON

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

Abstract translation: 公开了制造半导体器件的方法。 该方法可以包括在衬底上形成目标层，在目标层上形成掩模图案，执行蚀刻目标层并形成第一子沟槽的第一工艺，以及执行第二工艺以进一步蚀刻目标层和 形成第二子沟槽。 第一和第二侧壁图案可分别形成在掩模图案的侧壁上，以分别在第一和第二工艺中用作蚀刻掩模。 第一和第二侧壁图案的外侧壁可以形成为相对于基板的顶表面具有不同的角度。