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    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    1.
    发明申请
    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220059442A1

    公开(公告)日：2022-02-24

    申请号：US17230511

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538

    Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

    SEMICONDUCTOR PACKAGE
    2.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250046747A1

    公开(公告)日：2025-02-06

    申请号：US18417810

    申请日：2024-01-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyun KWEON ,  Wooju KIM ,  Kangil YUN ,  Junho YOON ,  Dayoung CHO ,  Jinwook HONG

    IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate and including a first chip pad and a first upper insulating layer on sidewalls of the first chip pad, a first bonding wire on a top surface of the first chip pad and connected to the first chip pad, and a second semiconductor chip on a top surface of the first semiconductor chip and spaced apart from the first chip pad, wherein the second semiconductor chip includes a second semiconductor die and a second lower insulating layer on a bottom surface of the second semiconductor die, wherein the second lower insulating layer may be directly bonded to the first upper insulating layer by a chemical bond between the first upper insulating layer and the second lower insulating layer.

    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE
    4.
    发明公开
    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230260845A1

    公开(公告)日：2023-08-17

    申请号：US17896578

    申请日：2022-08-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyun KWEON ,  YeongBeom KO ,  Wooju KIM ,  Heejae NAM ,  Jungseok RYU ,  Junho YOON

    IPC: H01L21/8234 ,  H01L23/00

    CPC classification number: H01L21/823437 ,  H01L21/823475 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16145

    Abstract: Disclosed are wafer structures and semiconductor devices. A semiconductor device may include a substrate and a cell array structure on the substrate. The substrate may include a device region and a dummy region surrounding the device region in a plan view. The cell array structure may include a plurality of first dielectric layers, a plurality of gate structures, a vertical channel structure, and a dummy pattern. The vertical channel structure may be on the device region and may penetrate the plurality of gate structures and the plurality of first dielectric layers. The cell array structure includes an outer sidewall above an edge of the substrate and a recessed portion on the outer sidewall of the cell array structure. The dummy pattern may cover a sidewall of the recessed portion and a bottom surface of the recessed portion. The dummy pattern and vertical channel structure may include a same material.

    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE
    6.
    发明申请
    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230073690A1

    公开(公告)日：2023-03-09

    申请号：US17711370

    申请日：2022-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

    Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    8.
    发明申请
    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220068779A1

    公开(公告)日：2022-03-03

    申请号：US17308643

    申请日：2021-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Jeonggi JIN ,  Hyunsu HWANG

    IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

    Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

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