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    MEMORY, MEMORY SYSTEM, AND ERROR CHECKING AND CORRECTING METHOD FOR MEMORY
    2.
    发明申请
    MEMORY, MEMORY SYSTEM, AND ERROR CHECKING AND CORRECTING METHOD FOR MEMORY 有权
    存储器，存储器系统以及存储器的错误检查和校正方法

    公开(公告)号：US20130198577A1

    公开(公告)日：2013-08-01

    申请号：US13648421

    申请日：2012-10-10

    申请人： Samsung Electronics Co., Ltd.

    发明人： Eun-chu OH ,  Jae-hong KIM ,  Jun-jin KONG

    IPC分类号： H03M13/05

    CPC分类号： H03M13/05 ,  H03M13/1102 ,  H03M13/356 ,  H03M13/3707

    摘要： A memory system includes an error checking and correction (ECC) engine configured to perform error checking and correction of data temporarily stored in a first memory array and data read out from the first memory array according to a first method, and perform error checking and correction of data stored in a second memory array after read out from the first memory array and data read out from the second memory array according to a second method, wherein the first method and the second method are selected in response to a control signal having at least a first logic level, and the second method checks and corrects data errors occurring at a higher rate compared the first method.

    摘要翻译： 存储器系统包括错误检查和校正（ECC）引擎，其被配置为根据第一方法执行临时存储在第一存储器阵列中的数据的错误校验和校正以及从第一存储器阵列读出的数据，并执行错误校验和校正 根据第二方法从第一存储器阵列读出并从第二存储器阵列读出的数据中存储在第二存储器阵列中的数据，其中响应于至少具有至少一个控制信号的控制信号选择第一方法和第二方法 第一种逻辑级别，第二种方法检查和纠正以比较第一种方法更高速率发生的数据错误。

    LIST DECODING METHOD FOR POLAR CODE AND MEMORY SYSTEM USING THE SAME
    3.
    发明申请
    LIST DECODING METHOD FOR POLAR CODE AND MEMORY SYSTEM USING THE SAME 有权
    使用相同的极性代码和存储器系统的列表解码方法

    公开(公告)号：US20150263767A1

    公开(公告)日：2015-09-17

    申请号：US14645073

    申请日：2015-03-11

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dong-Min SHIN ,  Jun-jin KONG ,  Ki-Jun LEE ,  Myung-Kyu LEE ,  Kyeong-Cheol YANG ,  Seung-Chan LIM

    IPC分类号： H03M13/45

    CPC分类号： H03M13/13 ,  H03M13/134

    摘要： A list decoding method for a polar code includes generating a tree-type decoding graph for input codeword symbols; the generating a tree-type decoding graph including, generating a decoding path list to which a decoding edge is added based on a reliability of a decoding path, the decoding path list being generated such that, among decoding paths generated based on the decoding edge, decoding paths within a threshold number of critical paths survive within the decoding path list in an order of high likelihood probability, and determining an estimation value, which corresponds to a decoding path having a maximum likelihood probability from among decoding paths of the decoding path list, as an information word.

    摘要翻译： 用于极性码的列表解码方法包括：生成用于输入码字符号的树型解码图; 生成树型解码图，包括：基于解码路径的可靠性生成解码边缘被添加到的解码路径列表，生成解码路径列表，使得在基于解码边缘生成的解码路径中， 在所述解码路径列表内以高似然概率的顺序在阈值数量的关键路径内解码路径，并且从所述解码路径列表的解码路径中确定对应于具有最大似然概率的解码路径的估计值， 作为信息词。

    MEMORY CONTROLLERS AND FLASH MEMORY READING METHODS
    4.
    发明申请
    MEMORY CONTROLLERS AND FLASH MEMORY READING METHODS 有权
    存储控制器和闪存存储器读取方法

    公开(公告)号：US20150220389A1

    公开(公告)日：2015-08-06

    申请号：US14601659

    申请日：2015-01-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kyung-jin KIM ,  Ung-hwan KIM ,  Eun-cheol KIM ,  Jun-jin KONG ,  Se-jin LIM

    IPC分类号： G06F11/10 ,  H03M13/37

    CPC分类号： H03M13/3738 ,  G06F11/1048 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/3715 ,  H03M13/3746

    摘要： A method of reading multi-bit data stored in a memory cell of a flash memory includes attempting to perform hard decision (HD) decoding on output data from the flash memory, and performing soft decision (SD) decoding on the output data when the HD decoding cannot be performed. The performing of the SD decoding includes: changing a maximum number of iterations according to a threshold voltage distribution of the memory cell; and performing the SD decoding based on the changed maximum number of iterations.

    摘要翻译： 读取存储在闪速存储器的存储单元中的多位数据的方法包括尝试对来自闪速存储器的输出数据执行硬判决（HD）解码，以及当HD处理时对输出数据执行软判决（SD）解码 无法执行解码。 SD解码的执行包括：根据存储器单元的阈值电压分布来改变最大迭代次数; 以及基于改变的最大迭代次数执行SD解码。

    METHOD OF OPERATING CYCLIC REDUNDANCY CHECK IN MEMORY SYSTEM AND MEMORY CONTROLLER USING THE SAME
    6.
    发明申请
    METHOD OF OPERATING CYCLIC REDUNDANCY CHECK IN MEMORY SYSTEM AND MEMORY CONTROLLER USING THE SAME 有权
    在存储器系统中操作循环冗余校验的方法和使用其的存储器控​​制器

    公开(公告)号：US20140101513A1

    公开(公告)日：2014-04-10

    申请号：US14045001

    申请日：2013-10-03

    申请人： Samsung Electronics Co., Ltd

    发明人： Nam-shik KIM ,  Dae-wook KIM ,  Bi-woong CHUNG ,  Jun-jin KONG

    IPC分类号： H03M13/09

    CPC分类号： H03M13/095 ,  G06F11/1004 ,  H03M13/09 ,  H03M13/091

    摘要： A method of performing a cyclic redundancy check (CRC) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (LFSR) circuit in a CRC polynomial, generating CRC parity information with respect to input data to be stored in a memory device by using the LFSR circuit, and generating a CRC code with respect to the input data based on the CRC parity information, such that the initialization of the LFSR circuit is set such that a register initial value of the LFSR circuit is determined to satisfy a condition that, when data input to the LFSR circuit is first state information, the CRC parity information generated from the LFSR circuit is second state information.

    摘要翻译： 在存储器系统中执行循环冗余校验（CRC）操作的方法和使用该循环冗余校验（CRC）的存储器控​​制器。 该方法包括以CRC多项式初始化线性反馈移位寄存器（LFSR）电路，通过使用LFSR电路产生关于要存储在存储器件中的输入数据的CRC奇偶校验信息，以及生成关于 基于CRC奇偶校验信息的输入数据，使得LFSR电路的初始化被设置为使得LFSR电路的寄存器初始值被确定为满足以下条件：当输入到LFSR电路的数据是第一状态信息时， 从LFSR电路产生的CRC奇偶校验信息是第二状态信息。