公开(公告)号：US20230085456A1

公开(公告)日：2023-03-16

申请号：US17859472

申请日：2022-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Suk Chae ,  Dongsik Kong ,  Youngwook Park ,  Jihoon Kim ,  Myung-Hyun Baek ,  Ju Hyung We ,  Jun-Bum Lee

IPC: H01L29/423 ,  H01L21/306 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

公开(公告)号：US12048143B2

公开(公告)日：2024-07-23

申请号：US17392775

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Ahn ,  Yongseok Ahn ,  Hyunyong Kim ,  Minsub Um ,  Ju Hyung We ,  Joonkyu Rhee ,  Yoonyoung Choi

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.

公开(公告)号：US11715666B2

公开(公告)日：2023-08-01

申请号：US17574665

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun Im ,  Kibum Lee ,  Daehyun Kim ,  Ju Hyung We ,  Sungmi Yoon

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/02 ,  H01L27/146 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H10B12/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02667 ,  H01L21/763 ,  H01L21/8238 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/1463 ,  H01L29/785 ,  H10B12/053 ,  H10B12/482 ,  H10B41/27 ,  H10B43/27 ,  H01L21/02532 ,  H01L21/02592

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

公开(公告)号：US11232973B2

公开(公告)日：2022-01-25

申请号：US16728348

申请日：2019-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyun Im ,  Kibum Lee ,  Daehyun Kim ,  Ju Hyung We ,  Sungmi Yoon

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/02 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/108 ,  H01L27/146 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.