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公开(公告)号:US20240135523A1
公开(公告)日:2024-04-25
申请号:US18486350
申请日:2023-10-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taesoo Shin , Seulgi Ok , Kibum Lee , Sungwook Hwang
IPC: G06T7/00
CPC classification number: G06T7/0004 , G06T2207/30148
Abstract: A method of predicting a semiconductor yield includes receiving wafer level data generated by measuring a plurality of wafers, generating a plurality of virtual chips corresponding to the plurality of wafers based on the wafer level data, mapping a test result of the plurality of wafers to the plurality of virtual chips, computing a defect rate of the plurality of virtual chips according to defects based on a result of the mapping, and computing a defect index of the equipment based on the defect rate.
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公开(公告)号:US20240127426A1
公开(公告)日:2024-04-18
申请号:US18204033
申请日:2023-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sungwook Hwang , Tae Soo Shin , Seulgi Ok , Kibum Lee
IPC: G06T7/00 , G06T7/60 , G06V10/141 , G06V10/60
CPC classification number: G06T7/001 , G06T7/60 , G06V10/141 , G06V10/60 , G06T2207/10061 , G06T2207/30148
Abstract: A test device includes a memory and a controller. The memory stores reference data including a reference image obtained by photographing a reference pattern on a first semiconductor sample, a first height of the reference pattern, a first shadow length of the reference pattern, and a reference value that represents a correlation between the first height and the first shadow length. The controller receives an image obtained by photographing a pattern on a second semiconductor sample, measures a second shadow length of the pattern from the image, and calculates a second height of the pattern from the second shadow length based on the reference data.
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公开(公告)号:US11715666B2
公开(公告)日:2023-08-01
申请号:US17574665
申请日:2022-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Hyun Im , Kibum Lee , Daehyun Kim , Ju Hyung We , Sungmi Yoon
IPC: H01L21/762 , H01L21/763 , H01L21/02 , H01L27/146 , H01L29/78 , H01L21/8238 , H01L21/8234 , H10B12/00 , H10B41/27 , H10B43/27
CPC classification number: H01L21/76224 , H01L21/02238 , H01L21/02667 , H01L21/763 , H01L21/8238 , H01L21/823481 , H01L21/823878 , H01L27/1463 , H01L29/785 , H10B12/053 , H10B12/482 , H10B41/27 , H10B43/27 , H01L21/02532 , H01L21/02592
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.
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公开(公告)号:US11232973B2
公开(公告)日:2022-01-25
申请号:US16728348
申请日:2019-12-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dong-Hyun Im , Kibum Lee , Daehyun Kim , Ju Hyung We , Sungmi Yoon
IPC: H01L21/762 , H01L21/763 , H01L21/02 , H01L27/11556 , H01L27/11582 , H01L21/8234 , H01L27/108 , H01L27/146 , H01L29/78 , H01L21/8238
Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.
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