公开(公告)号：US20240147706A1

公开(公告)日：2024-05-02

申请号：US18370149

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keunui KIM ,  Kiseok LEE ,  Eunsuk JANG ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Moonyoung JEONG

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate, a bit line extending in a first direction on the substrate, a first word line and a second word line extending in a second direction to cross the bit line, a back-gate electrode extending in the second direction between the first word line and the second word line, first and second active patterns disposed between the first and second word lines and the back-gate electrode and connected to the bit line, contact patterns coupled to the first and second active patterns, respectively, a first back-gate capping pattern between the contact patterns and the back-gate electrode, and first gate capping patterns between the contact patterns and the first and second word lines. The first back-gate capping pattern and the first gate capping pattern may have first and second seams, which are extended in the second direction and are located at different vertical levels.

公开(公告)号：US20240147701A1

公开(公告)日：2024-05-02

申请号：US18238790

申请日：2023-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Eunju CHO ,  Keunnam KIM ,  Seokhan PARK ,  Seok-Ho SHIN ,  Joongchan SHIN ,  Heechan YOON

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor memory device may include a substrate including a cell array region and a connection region, bit lines provided on the substrate and extending in a first direction, first and second active patterns alternately arranged in the first direction on each of the bit lines, back-gate electrodes disposed between adjacent ones of the first and second active patterns and extended in a second direction to cross the bit lines, first and second word lines disposed adjacent to the first and second active patterns respectively and extending in the second direction, and a shielding conductive pattern including line portions, which are respectively disposed between adjacent ones of the bit lines, and a plate portion, which is connected in common to the line portions. A length of the line portions of the shielding conductive pattern in the first direction may be shorter than that of the bit lines.

公开(公告)号：US20250107075A1

公开(公告)日：2025-03-27

申请号：US18809859

申请日：2024-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan KIM ,  Joongchan SHIN ,  Hyungeun CHOI ,  Taegyu KANG ,  Keunui KIM ,  Bowon YOO

IPC: H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array area and an interface area, bit lines on the cell array area and extending in a first horizontal direction, back gate lines on the bit lines and extending in a second direction, insulating blocks on the interface area and each overlapping the back gate lines in the second direction, word lines among which each pair of two adjacent word lines are on both sides of a corresponding back gate line, respectively, and extending on a sidewall of a corresponding insulating block, active semiconductor layers each between a corresponding back gate line and a corresponding word line on the cell array area and having one end electrically connected to a corresponding bit line, and a word line contact on the interface area and on a corresponding word line and a corresponding insulating block adjacent thereto.

公开(公告)号：US20220085023A1

公开(公告)日：2022-03-17

申请号：US17471778

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokho SHIN ,  Taegyu KANG ,  Byeungmoo KANG ,  Joongchan SHIN

IPC: H01L27/108

Abstract: A semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode and including a pair of convex surfaces in contact with the semiconductor pattern.

公开(公告)号：US20240422961A1

公开(公告)日：2024-12-19

申请号：US18640513

申请日：2024-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H10B12/00

Abstract: A semiconductor memory device includes a plurality of word lines extending in a first horizontal direction, a plurality of back gate lines extending in the first horizontal direction and alternately arranged with the plurality of word lines in a second horizontal direction different from the first horizontal direction, a plurality of channel layers extending in a vertical direction between a word line and a back gate line adjacent to each other among the plurality of word lines and the plurality of back gate lines, to correspond to columns in the first horizontal direction, a plurality of bit lines extending in the second horizontal direction on the plurality of word lines, the plurality of back gate lines, and the plurality of channel layers and electrically connected to the plurality of channel layers, and a plurality of memory structures electrically connected to the plurality of channel layers.

公开(公告)号：US20240421223A1

公开(公告)日：2024-12-19

申请号：US18631839

申请日：2024-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

IPC: H01L29/78 ,  H10B12/00

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US20220173106A1

公开(公告)日：2022-06-02

申请号：US17369320

申请日：2021-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungeun CHOI ,  Kiseok LEE ,  Seungjae JUNG ,  Joongchan SHIN ,  Taehyun AN ,  Moonyoung JEONG ,  Sangyeon HAN

IPC: H01L27/108 ,  H01L29/08

Abstract: A semiconductor memory device includes: a bit line extending on a substrate in a vertical direction; a transistor body part including a first source-drain region, a monocrystalline channel layer, and a second source-drain region that are sequentially arranged in a first horizontal direction and connected to the bit line; gate electrode layers extending in a second horizontal direction that is orthogonal to the first horizontal direction, with a gate dielectric layer between the gate electrode layers and the monocrystalline channel layer, and covering upper and lower surfaces of the monocrystalline channel layer; and a cell capacitor including a lower electrode layer, a capacitor dielectric layer, and an upper electrode layer at a side of the transistor body that is opposite to the bit line in the first horizontal direction and is connected to the second source-drain region.

公开(公告)号：US20250107071A1

公开(公告)日：2025-03-27

申请号：US18671624

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Keunui KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Gyuhwan OH ,  Bowon YOO ,  Kiseok LEE ,  Sangho LEE ,  Eunsuk JANG ,  Moonyoung JEONG

IPC: H10B12/00

Abstract: A semiconductor device comprising: a substrate; bit lines on the substrate; word lines on the bit lines, wherein the word lines are spaced apart from each other in a first direction; activation patterns between the word lines; a back gate electrode between the activation patterns, wherein the back gate electrode extends in a second direction; and a first gate separation pattern between the word lines in the first direction, wherein a portion of the word lines is a space between the activation patterns in the second direction and the word lines extend around the activation patterns, wherein the word lines and the first gate separation pattern each include a first surface facing the bit lines and a second surface opposite to the first surface in a third direction, wherein the first gate separation pattern is closer than the word lines to the bit lines in the third direction.

公开(公告)号：US20240147707A1

公开(公告)日：2024-05-02

申请号：US18242817

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taegyu KANG ,  Taehyuk KIM ,  Seok-Ho SHIN ,  Keunnam KIM ,  Seokhan PARK ,  Joongchan SHIN ,  Kiseok LEE

IPC: H10B12/00 ,  H01L23/522

CPC classification number: H10B12/50 ,  H01L23/5225 ,  H10B12/09 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device may include a substrate including a cell array region and a peripheral circuit region, an active pattern on the cell array region of the substrate, a peripheral active pattern on the peripheral circuit region of the substrate, a peripheral gate electrode disposed on a top surface of the peripheral active pattern, a first interlayer insulating pattern provided on the cell array region to cover a top surface of the active pattern, a first etch stop layer covering the first interlayer insulating pattern and the peripheral gate electrode with a uniform thickness, and a second interlayer insulating pattern disposed on the first etch stop layer and in the peripheral circuit region. In the cell array region, the second interlayer insulating pattern may have a top surface, which is located at substantially the same level as a top surface of the first etch stop layer.

公开(公告)号：US20240098984A1

公开(公告)日：2024-03-21

申请号：US18368243

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungeun CHOI ,  Seokho SHIN ,  Joongchan SHIN ,  Kiseok LEE ,  Keunnam KIM ,  Seokhan PARK ,  Eunsuk JANG ,  Jinwoo HAN

IPC: H10B12/00 ,  H01L29/78

CPC classification number: H10B12/482 ,  H01L29/7827 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor device may include a substrate, a bitline extending in a first direction on the substrate, and an active pattern on the bitline. The semiconductor device may include a back gate electrode extending beside one side of the active pattern in a second direction perpendicular to the first direction across the bitline, and a wordline extending in the second direction beside the other side of the active pattern. A length of the active pattern in the second direction may be greater than a length of the bitline in the second direction.