知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.021 seconds)

    Methods of Manufacturing Semiconductor Devices
    1.
    发明申请
    Methods of Manufacturing Semiconductor Devices 有权
    制造半导体器件的方法

    公开(公告)号：US20130149833A1

    公开(公告)日：2013-06-13

    申请号：US13705320

    申请日：2012-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Hyoung Choi ,  Ki Yeon Park ,  Joon Kim ,  Cha Young Yoo ,  Youn Soo Kim ,  Ho Jun Kwon ,  Sang Yeol Kang

    IPC: H01L49/02

    CPC classification number: H01L28/60 ,  H01L28/92

    Abstract: A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

    Abstract translation: 一种制造半导体器件的方法，所述方法包括：制备包括模层和设置在所述模层上的支撑层的半导体衬底; 形成穿过模层和支撑层的多个孔; 在孔中形成多个底部电极; 通过去除模具层的至少一部分来暴露至少一部分底部电极; 从底部电极的暴露表面去除一部分底部电极; 并且在底部电极上依次形成电介质层和顶部电极层。

    Semiconductor devices including data storage patterns
    2.
    发明授权
    Semiconductor devices including data storage patterns 有权

    公开(公告)号：US10833124B2

    公开(公告)日：2020-11-10

    申请号：US15953573

    申请日：2018-04-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyo Seop Kim ,  Chang Woo Sun ,  Gyu Hwan Oh ,  Joon Kim ,  Joon Youn Hwang

    IPC: H01L23/525 ,  H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.

    Semiconductor devices having hybrid capacitors and methods for fabricating the same
    4.
    发明授权
    Semiconductor devices having hybrid capacitors and methods for fabricating the same 有权
    具有混合电容器的半导体器件及其制造方法

    公开(公告)号：US09053971B2

    公开(公告)日：2015-06-09

    申请号：US14052097

    申请日：2013-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongkyun Park ,  Han-Young Kim ,  Joon Kim ,  Hyun Park ,  Junghwan Oh ,  Minhee Cho

    IPC: H01L21/02 ,  H01L29/94 ,  H01L27/108 ,  H01L21/20 ,  H01L49/02

    CPC classification number: H01L28/91 ,  H01L21/28562 ,  H01L21/31116 ,  H01L27/10852

    Abstract: A semiconductor device includes a plurality of capacitors disposed on a substrate and a support pattern supporting upper portions and lower portions of the capacitors. Each of the capacitors includes a lower electrode, an upper electrode, and a dielectric layer between the lower and upper electrodes. The lower electrode includes a first electrode portion electrically connected to the substrate and having a solid shape and a second electrode portion stacked on the first electrode portion and having a shape comprising an opening therein. The support pattern includes an upper pattern contacting sidewalls of top end portions of the lower electrodes and a lower pattern vertically spaced apart from the upper pattern. The lower pattern contacts sidewalls under the top end portions of the lower electrodes.

    Abstract translation: 半导体器件包括设置在基板上的多个电容器和支撑电容器的上部和下部的支撑图案。 每个电容器包括在下电极和上电极之间的下电极，上电极和电介质层。 下电极包括电连接到基板并具有固体形状的第一电极部分和堆叠在第一电极部分上并具有包括其中的开口的形状的第二电极部分。 支撑图案包括接触下部电极的顶端部的侧壁的上部图案和与上部图案垂直间隔开的下部图案。 下部图案接触下部电极的顶端部分的侧壁。

    Methods for forming fine patterns of a semiconductor device
    5.
    发明授权
    Methods for forming fine patterns of a semiconductor device 有权
    用于形成半导体器件的精细图案的方法

    公开(公告)号：US08785319B2

    公开(公告)日：2014-07-22

    申请号：US13799125

    申请日：2013-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon-Soo Park ,  Kukhan Yoon ,  Joon Kim ,  Cheolhong Kim ,  Seokwoo Nam

    IPC: H01L21/4763

    CPC classification number: H01L21/3083 ,  H01L21/0331 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/10817 ,  H01L27/10891 ,  H01L27/11556 ,  H01L27/24 ,  H01L28/91

    Abstract: Methods of forming fine patterns are provided. The methods may include forming first hard mask patterns extending in a first direction on a lower layer, forming second hard mask patterns filling gap regions between the first hard mask patterns, forming first mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the first mask patterns as etch masks to form first openings, forming second mask patterns filling the first openings and extending in the second direction, and etching the second hard mask patterns using the second mask patterns as etch masks to form second openings spaced apart from the first openings in a diagonal direction with respect to the first direction.

    Abstract translation: 提供形成精细图案的方法。 所述方法可以包括形成在下层上沿着第一方向延伸的第一硬掩模图案，形成填充第一硬掩模图案之间的间隙区域的第二硬掩模图案，形成沿垂直于第一方向的第二方向延伸的第一掩模图案 第一和第二硬掩模图案，使用第一掩模图案蚀刻第一硬掩模图案作为蚀刻掩模以形成第一开口，形成填充第一开口并在第二方向上延伸的第二掩模图案，以及使用 第二掩模图案作为蚀刻掩模，以在相对于第一方向的对角线方向上形成与第一开口间隔开的第二开口。

    Image sensor including color filters
    6.
    发明授权
    Image sensor including color filters 有权

    公开(公告)号：US10784314B2

    公开(公告)日：2020-09-22

    申请号：US16555074

    申请日：2019-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong Hyun Yoo ,  Eun Mi Kim ,  Joon Kim ,  Chang Hwa Kim ,  Sang Su Park ,  Kyung Rae Byun ,  Sang Hoon Song

    IPC: H01L27/146 ,  H01L27/30 ,  H01L27/28 ,  H01L31/0224 ,  H01L31/0216 ,  H01L51/42

    Abstract: The present invention relates to image sensors and method of manufacturing the same. The image sensor may include a substrate having pixel regions in which photoelectric-conversion devices and storage node regions spaced apart from each other; a lower contact via between the photoelectric conversion-devices in the pixel regions; a first insulating layer on the lower contact via and having an opening; an upper contact via electrically connected to the lower contact via through the first insulating layer and protruding from the first insulating layer; a second insulating layer surrounding the first insulating layer and the upper contact via, an upper surface of the second insulating layer in the opening defining a trench; a color filter filling the trench; a protective film exposing the upper contact via; a first transparent electrode on the protective film that contacts the upper contact via; and an organic photoelectric layer on the first transparent electrode.

    Semiconductor device with vertical channel transistor and method of fabricating the same
    7.
    发明授权
    Semiconductor device with vertical channel transistor and method of fabricating the same 有权
    具有垂直沟道晶体管的半导体器件及其制造方法

    公开(公告)号：US08883596B2

    公开(公告)日：2014-11-11

    申请号：US13790076

    申请日：2013-03-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seonghwee Cheong ,  Mansug Kang ,  Joon Kim ,  Kihong Nam ,  Gyuwan Choi

    IPC: H01L29/66 ,  H01L27/108 ,  H01L27/105 ,  H01L27/22 ,  H01L27/24

    CPC classification number: H01L29/66666 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/228 ,  H01L27/2454

    Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.

    Abstract translation: 提供了具有垂直沟道晶体管的半导体器件及其制造方法。 一种制造半导体器件的方法包括图案化衬底以形成限定有源区的沟槽，在沟槽的下部区域中形成牺牲图案，在沟槽的上侧壁上形成间隔物，使沟槽的顶面凹陷 牺牲图案以形成暴露间隔物和牺牲图案之间的有源区域的侧壁的窗口，通过窗口掺杂沟槽的侧壁以在有源区域中形成掺杂区域，以及在待连接的沟槽中形成布线 到掺杂区域。

    Methods of manufacturing semiconductor devices
    8.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08790986B2

    公开(公告)日：2014-07-29

    申请号：US13705320

    申请日：2012-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Hyoung Choi ,  Ki Yeon Park ,  Joon Kim ,  Cha Young Yoo ,  Youn Soo Kim ,  Ho Jun Kwon ,  Sang Yeol Kang

    IPC: H01L21/20

    CPC classification number: H01L28/60 ,  H01L28/92

    Abstract: A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

    Abstract translation: 一种制造半导体器件的方法，所述方法包括：制备包括模层和设置在所述模层上的支撑层的半导体衬底; 形成穿过模层和支撑层的多个孔; 在孔中形成多个底部电极; 通过去除模具层的至少一部分来暴露至少一部分底部电极; 从底部电极的暴露表面去除一部分底部电极; 并且在底部电极上依次形成电介质层和顶部电极层。

Patent Agency Ranking