Abstract:
An image sensor is disclosed. The image sensor includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharges generated from the photodiode; a first capacitor configured to store charges according to a voltage of the floating diffusion node which is reset; a second capacitor configured to store charges according to a voltage of the floating diffusion node in which the photocharges are accumulated; a first sampling transistor connected to a first output node and configured to sample charges to the first capacitor; a second sampling transistor connected to the first output node and configured to sample charges to the second capacitor; and at least one precharge select transistor connected to the first output node and configured to reset the first output node.
Abstract:
An image sensor is disclosed. The image sensor includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharges generated from the photodiode; a first capacitor configured to store charges according to a voltage of the floating diffusion node which is reset; a second capacitor configured to store charges according to a voltage of the floating diffusion node in which the photocharges are accumulated; a first sampling transistor connected to a first output node and configured to sample charges to the first capacitor; a second sampling transistor connected to the first output node and configured to sample charges to the second capacitor; and at least one precharge select transistor connected to the first output node and configured to reset the first output node.
Abstract:
An image sensor is disclosed. The image sensor includes a plurality of pixels arranged in a plurality of rows and a plurality of columns, each of the pixels including: a photodiode; a floating diffusion node configured to accumulate photocharges generated from the photodiode; a first capacitor configured to store charges according to a voltage of the floating diffusion node which is reset; a second capacitor configured to store charges according to a voltage of the floating diffusion node in which the photocharges are accumulated; a first sampling transistor connected to a first output node and configured to sample charges to the first capacitor; a second sampling transistor connected to the first output node and configured to sample charges to the second capacitor; and at least one precharge select transistor connected to the first output node and configured to reset the first output node.
Abstract:
An image sensor including: first and second capacitors; a first transistor between a photodiode and a floating diffusion node, and receiving a transfer signal; a second transistor between a first power terminal and the floating diffusion node and receiving a reset signal; a third transistor between a second power terminal and a first node and having a gate connected to the floating diffusion node; a fourth transistor between the first node and a column line and receiving a precharge signal; a fifth transistor between the first capacitor and a feedback node and receiving a first sampling signal; a sixth transistor between the second capacitor and feedback node and receiving a second sampling signal; a seventh transistor between the first node and feedback node and receiving a first switch signal; and an eighth transistor between the floating diffusion and feedback nodes and receiving a second switch signal.
Abstract:
A semiconductor device includes an active pillar that protrudes above a substrate, the active pillar including a pair of vertical sections and a body interconnection between the pair of vertical sections, and each of the pair of vertical sections having a channel body and a lower impurity region below the channel body, word lines coupled to respective channel bodies, and buried bit lines in contact with respective lower impurity regions, wherein the channel bodies are connected to the substrate through the body interconnection.
Abstract:
Provided are a pixel array and an image sensor. The pixel array includes a plurality of pixels, which are arranged in a matrix form and which convert an optical signal into an electrical signal. The pixel array includes a first pixel arranged in a first row of the pixel array and a second pixel arranged in a second row of the pixel array, wherein each of the first pixel and the second pixel includes a first memory storing a digital reset value according to internal noise, the first memory of the first pixel stores m-bit data (where m is a natural number equal to or greater than 2), and the first memory of the second pixel stores n-bit data (where n is a natural number less than m).
Abstract:
An earphone connection interface is provided. The earphone connection interface includes a first detector disposed at a first area to detect an electrical change according to a contact state of the first area, and a second detector disposed at a second area different from the first area to detect an electrical change according to a contact state of the second area
Abstract:
An image sensor according to some example embodiments of the present inventive concepts may operate in a global shutter mode, and each pixel circuit may support a high conversion gain (HCG) mode and a low conversion gain (LCG) mode so as to have high dynamic range (HDR). Accordingly, the image sensor according to some example embodiments of the present inventive concepts may have HDR and may generate a high-quality image.
Abstract:
An image sensor includes a plurality of pixels. Each of the plurality of pixels includes a photodetector that includes a photoelectric conversion element that outputs a detection signal in response to light incident thereon, a comparator that compares the detection signal of the photodetector with a ramp signal and outputs a comparison signal in response thereto, a plurality of first memory cells that store a first counting value corresponding to a first voltage level of the detection signal using the comparison signal of the comparator and output the first counting value through a plurality of transmission lines, and a plurality of second memory cells that store a second counting value corresponding to a second voltage level of the detection signal using the comparison signal of the comparator and output the second counting value through the plurality of transmission lines.
Abstract:
A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate, a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction, a gate spacer between the first gate electrode and the second gate electrode, and source/drain regions in the active region at opposite sides of the first gate electrode. The source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and, when viewed in a plan view, the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.