公开(公告)号：US10593670B2

公开(公告)日：2020-03-17

申请号：US15697720

申请日：2017-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo Na

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

公开(公告)号：US10529816B2

公开(公告)日：2020-01-07

申请号：US15915508

申请日：2018-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/772 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US09929252B2

公开(公告)日：2018-03-27

申请号：US15133548

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-gyu Choi ,  Sang-jin Hyun ,  Taek-soo Jeon ,  Hoon-joo Na ,  Young-suk Chai

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  C23C16/02 ,  C23C16/40

CPC classification number: H01L29/66795 ,  C23C16/0218 ,  C23C16/405 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28255 ,  H01L21/324 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/78642

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

公开(公告)号：US09806075B2

公开(公告)日：2017-10-31

申请号：US15001283

申请日：2016-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-yeol Song ,  Wan-don Kim ,  Oh-seong Kwon ,  Hyeok-jun Son ,  Sang-jin Hyun ,  Hoon-joo Na

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/0653 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

公开(公告)号：US20150093888A1

公开(公告)日：2015-04-02

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/51

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Abstract translation: 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US11588039B2

公开(公告)日：2023-02-21

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong Lee ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786 ,  H01L21/28 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/822 ,  H01L21/84

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US20200098882A1

公开(公告)日：2020-03-26

申请号：US16694242

申请日：2019-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-hyeong LEE ,  Hoon-joo Na ,  Sung-in Suh ,  Min-woo Song ,  Byoung-hoon Lee ,  Hu-yong Lee ,  Sang-jin Hyun

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L27/088 ,  B82Y10/00 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L21/822 ,  H01L29/06 ,  H01L29/786 ,  H01L21/28

Abstract: A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

公开(公告)号：US09236313B2

公开(公告)日：2016-01-12

申请号：US14563420

申请日：2014-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/51 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.