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公开(公告)号:US20240389348A1
公开(公告)日:2024-11-21
申请号:US18417089
申请日:2024-01-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungmin Park , Hanjin Lim , Ji-Sung Kim , Hyungsuk Jung
Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a lower electrode, a dielectric layer on the lower electrode, an upper electrode on the dielectric layer, and a defect preventing layer between the lower electrode and the upper electrode. The defect preventing layer includes at least one of a first defect preventing layer between the lower electrode and the dielectric layer or a second defect preventing layer between the upper electrode and the dielectric layer. The dielectric layer includes a ferroelectric layer that includes at least one of a ferroelectric material or an anti-ferroelectric material. The ferroelectric layer includes a polarization region and a non-polarization region surrounded by the polarization region.
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公开(公告)号:US20240008254A1
公开(公告)日:2024-01-04
申请号:US18116071
申请日:2023-03-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jungmin Park , Hanjin Lim , Hyungsuk Jung
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/033
Abstract: A semiconductor device includes a substrate, a lower electrode above the substrate, the lower electrode extending in a vertical direction, a support surrounding a side wall of the lower electrode and supporting the lower electrode, a dielectric layer on the lower electrode and the support, and an upper electrode on the dielectric layer, wherein the lower electrode includes a base electrode layer and an insertion layer, the base electrode layer containing a halogen element, and the insertion layer containing carbon, and the insertion layer is inserted in a portion of the lower electrode, the portion of the lower electrode being adjacent to the support and the dielectric layer.
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公开(公告)号:US20230253445A1
公开(公告)日:2023-08-10
申请号:US17993943
申请日:2022-11-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hongsik Chae , Taekyun Kim , Jinsu Lee , Yirang Lim , Hanjin Lim , Hyungsuk Jung
IPC: H10B12/00
CPC classification number: H01L28/75 , H01L28/91 , H10B12/315 , H01L28/92 , H10B12/0335
Abstract: A semiconductor device includes: a substrate; a contact plug on the substrate; a lower electrode electrically connected to the contact plug, and including a first electrode layer, a first buffer layer, and a second electrode layer, sequentially stacked; a first support layer in contact with an upper surface of the lower electrode and disposed to overlap at least a portion of the lower electrode, the first support layer extending in a direction parallel to an upper surface of the substrate; a dielectric layer disposed on the lower electrode and the first support layer; and an upper electrode disposed on the dielectric layer. The lower electrode comprises a first region overlapping the first support layer, and having a first height; and a second region not overlapping the first support layer, and having a second height lower than the first height.
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公开(公告)号:US09337149B2
公开(公告)日:2016-05-10
申请号:US14681313
申请日:2015-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dong-Hyun Im , Hyun Park , Soongun Lee , Chang Seok Lee , Sangwon Kim , Seongjun Park , Hyeon Jin Shin , Hanjin Lim
IPC: H01L27/02 , H01L23/532 , H01L27/108 , H01L23/528 , H01L21/02 , H01L21/3213 , H01L29/06 , H01L21/768
CPC classification number: H01L23/53276 , H01L21/02527 , H01L21/32139 , H01L21/768 , H01L21/76834 , H01L21/7685 , H01L21/76852 , H01L21/76885 , H01L23/528 , H01L23/53209 , H01L23/53214 , H01L23/53223 , H01L23/53228 , H01L23/53238 , H01L23/53257 , H01L23/53266 , H01L23/53271 , H01L27/10814 , H01L27/10852 , H01L27/10855 , H01L27/10873 , H01L27/10885 , H01L27/10888 , H01L29/0642 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern.
Abstract translation: 半导体器件可以包括:衬底,其包括由器件隔离层限定的有源区,有源区中的源极/漏极区,在与有源区平行的第一方向上延伸的并且沿与第一方向交叉的第二方向布置的字线; 在第二方向上延伸并与位于字线之间的有源区的一部分交叉的位线图形,以及覆盖位线图案的至少一部分的石墨烯图案。
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公开(公告)号:US20240357832A1
公开(公告)日:2024-10-24
申请号:US18512331
申请日:2023-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok Lee , Jinwoo Han , Hanjin Lim
Abstract: A semiconductor device includes a bit line structures on a substrate, extending in a first direction, and being spaced apart from each other in a second direction; channels contacting upper surfaces of the bit line structures and being spaced apart from each other in the first and second directions; upper gate structures extending in the second direction and surrounding the channels disposed in the second direction, the upper gate structures being spaced apart in the first direction; and a capacitor structure including first capacitor electrodes respectively on the channels; a dielectric layer on the first capacitor electrodes, the dielectric layer including a ferroelectric material or an anti-ferroelectric material; a second capacitor electrode layer on the dielectric layer; and capacitor plate electrodes on the second capacitor electrode layer, the capacitor plate electrodes each extending in the second direction and being spaced apart from each other in the first direction.
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公开(公告)号:US20240321938A1
公开(公告)日:2024-09-26
申请号:US18591310
申请日:2024-02-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Cheoljin Cho , Yukyung Shin , Jieun Lee , Hanjin Lim , Changhwa Jung , Jayun Choi
IPC: H10B12/00
CPC classification number: H01L28/55 , H10B12/482 , H10B12/488
Abstract: A semiconductor device includes a lower electrode disposed on a substrate; a dielectric layer covering the lower electrode; and an upper electrode spaced apart from the lower electrode. The dielectric layer is disposed between the upper electrode and the lower electrode. A thickness of the dielectric layer is less than or equal to 6 nm, and a grain size in the dielectric layer is between 3 nm and 30 nm.
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公开(公告)号:US12057470B2
公开(公告)日:2024-08-06
申请号:US17809727
申请日:2022-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungmin Park , Hanjin Lim , Hyungsuk Jung
CPC classification number: H01L28/55 , H01L28/65 , H01L28/75 , H10B12/482 , H01L28/82
Abstract: A semiconductor device includes a capacitor. The capacitor includes a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction. The dielectric layer includes a first dielectric layer and a second dielectric layer that are interposed between the bottom electrode and the top electrode and are stacked in the first direction. The first dielectric layer is anti-ferroelectric, and the second dielectric layer is ferroelectric. A thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.
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公开(公告)号:US20230209804A1
公开(公告)日:2023-06-29
申请号:US17935148
申请日:2022-09-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Cheoljin Cho , Yukyung Shin , Changhwa Jung , Hyunjun Kim , Hanjin Lim
IPC: H01L27/108
CPC classification number: H01L27/10814 , H01L27/10823
Abstract: A capacitor is described. The capacitor includes a lower electrode, a dielectric layer structure disposed on the lower electrode, and an upper electrode disposed on the dielectric layer structure. The dielectric layer structure includes a first dielectric layer, a second dielectric layer contacting the first dielectric layer, and a third dielectric layer contacting the second dielectric layer. Each of the first to third dielectric layers includes a material with a crystalline structure. The second dielectric layer includes an oxide having ferroelectric or antiferroelectric properties, and the second dielectric layer includes a material in which at least two different crystal phases are mixed.
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公开(公告)号:US11621339B2
公开(公告)日:2023-04-04
申请号:US17390864
申请日:2021-07-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sunmin Moon , Young-Lim Park , Kyuho Cho , Hanjin Lim
IPC: H01L29/51 , H01L21/762 , H01L29/15 , H01L29/06 , H01L27/108 , H01L49/02
Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.
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公开(公告)号:US20240321943A1
公开(公告)日:2024-09-26
申请号:US18601032
申请日:2024-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jungmin Park , Hanjin Lim , Hyungsuk Jung
IPC: H10B12/00
CPC classification number: H01L28/75 , H01L28/65 , H10B12/31 , H10B12/482 , H10B12/488
Abstract: A semiconductor memory device includes an upper electrode, a lower electrode, an anti-ferroelectric layer disposed between the upper electrode and the lower electrode and including an anti-ferroelectric, an oxide layer disposed on a first surface of the anti-ferroelectric layer and including a high dielectric material, and a metal oxide layer disposed on a second surface of the anti-ferroelectric layer opposite to the first surface. A thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the anti-ferroelectric layer.
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