公开(公告)号：US20230422502A1

公开(公告)日：2023-12-28

申请号：US18202111

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seulji LEE ,  Jinhyuk Kim ,  Byoungil Lee ,  Sehoon Lee ,  Jinwoo Jeon

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.

公开(公告)号：US11621276B2

公开(公告)日：2023-04-04

申请号：US17035970

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hun Jeong ,  Byoungil Lee ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

公开(公告)号：US11164887B2

公开(公告)日：2021-11-02

申请号：US16749110

申请日：2020-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US12225730B2

公开(公告)日：2025-02-11

申请号：US17377840

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehoon Lee ,  Byoungil Lee

IPC: H10B43/35 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/46 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.

公开(公告)号：US20210375920A1

公开(公告)日：2021-12-02

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US12048159B2

公开(公告)日：2024-07-23

申请号：US18129145

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Hun Jeong ,  Byoungil Lee ,  Joonhee Lee

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

公开(公告)号：US11910600B2

公开(公告)日：2024-02-20

申请号：US17037532

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Jeong ,  Byoungil Lee ,  Bosuk Kang

IPC: H10B43/27 ,  H01L23/532 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/53257 ,  H01L23/53271 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer.

公开(公告)号：US11856773B2

公开(公告)日：2023-12-26

申请号：US17176398

申请日：2021-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yujin Seo ,  Euntaek Jung ,  Byoungil Lee ,  Seul Lee ,  Joonhee Lee ,  Changdae Jung ,  Bonghyun Choi ,  Sejie Takaki

IPC: H01L27/11582 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure. The second portion of the intermediate pattern layer has a side surface that is lowered while forming a surface curved from an upper surface of the first portion and that contacts the upper pattern layer.

公开(公告)号：US11792990B2

公开(公告)日：2023-10-17

申请号：US17514331

申请日：2021-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujin Seo ,  Byoungil Lee ,  Subin Kang ,  Jimo Gu

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical memory device includes channels on a substrate, a channel connecting pattern, gate electrodes, and an etch stop pattern and a blocking pattern sequentially stacked. The channels extend in a first direction perpendicular to an upper surface of the substrate. The channel connecting pattern extends in a second direction parallel to the upper surface of the substrate to cover outer sidewalls of the channels. The gate electrodes are spaced apart from each other in the first direction on the channel connecting pattern, and extend in the second direction to surround the channels. The etch stop pattern and the blocking pattern are sequentially stacked in a third direction parallel to the upper surface of the substrate and crossing the second direction on an end portion of the channel connecting pattern in the third direction, and include different materials from each other.

公开(公告)号：US20220115390A1

公开(公告)日：2022-04-14

申请号：US17377840

申请日：2021-07-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehoon Lee ,  Byoungil Lee

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11539 ,  H01L23/522

Abstract: Disclosed are three-dimensional semiconductor memory devices, methods of fabricating the same, and electronic systems including the same. The device includes a substrate including a cell array region and an extension region, stack structures extending in a first direction and including gate electrodes stacked on the substrate, vertical structures penetrating the stack structures on the cell array region, a mold structure on a portion of the extension region, a first support structure extending in the first direction between the stack structures, second support structures penetrating the stack structures on the extension region and spaced apart in a second direction from the first support structure, and a third support structure surrounding the mold structure in a plan view. Respective top surfaces of ones of the second support structures and a top surface of the third support structure is higher than a top surface of ones of the vertical structures.