Abstract:
A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.
Abstract:
A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.
Abstract:
A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.
Abstract:
According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.
Abstract:
A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.
Abstract:
According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.
Abstract:
A method of manufacturing a polarizer includes forming a first layer on a base substrate, forming a first partition wall layer on the first layer, forming a second partition wall layer on the first partition wall, forming a plurality of first partition wall patterns and a plurality of second partition walls disposed on the first partition wall patterns by etching the first partition wall and the second partition wall at the same time, forming a block copolymer layer on the first layer on which the plurality of first partition wall patterns are formed, forming a plurality of fine patterns from the block copolymer layer, and patterning the first layer using the fine patterns and the second partition wall patterns as a mask.
Abstract:
A display substrate includes a base substrate, a common line on the base substrate, a first insulation layer covering the common line and having a first insulating material, a conductive pattern on the first insulation layer and including a source electrode and a drain electrode, a second insulation layer covering the drain electrode and the common line, and including a lower second insulation layer having a second insulating material and an upper second insulation layer having the first insulating material, a first electrode electrically connected to the drain electrode through a first contact hole in the second insulation layer, and a second electrode electrically connected to the common line through a second contact hole in the first and second insulation layers. The upper and lower second insulation layers on the drain electrode have a first hole and a second hole respectively that form the first contact hole.
Abstract:
A thin film transistor includes a gate electrode, an active pattern over the gate electrode and including an oxide semiconductor, an etch-stop layer covering the active pattern, a source electrode on the etch-stop layer, a drain electrode on the etch-stop layer and spaced from the source electrode, and an active protection pattern between the etch-stop layer and the active pattern and electrically coupled to the source electrode and the drain electrode.