公开(公告)号：US20240274540A1

公开(公告)日：2024-08-15

申请号：US18647307

申请日：2024-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Dongbeen KIM ,  Jinwook KIM ,  Juhun PARK ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM

IPC: H01L23/535 ,  H01L23/00 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L24/13 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2224/13025

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

公开(公告)号：US20220336357A1

公开(公告)日：2022-10-20

申请号：US17521080

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Dongbeen KIM ,  Jinwook KIM ,  Juhun PARK ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/00 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/78

Abstract: A circuit chip including a substrate, first and second channel active regions on the substrate, and extending in a first direction, the second channel active regions spaced apart from the first channel regions in a second direction intersecting the first direction, first and second gate electrodes intersecting the second channel active regions, third and fourth gate electrodes intersecting the first channel active regions, and a contact electrode between the first, second, third, and fourth gate electrodes. The contact electrode including a stem section in a vertical direction, and first and second branch sections extending from the stem section and contacting a respective source/drain region on the first and second channel active regions, the first gate electrode and the third gate electrode overlapping in the second direction, and including edge portions having widths decreasing as the first gate electrode and the third gate electrode extend toward facing ends thereof.

公开(公告)号：US20220157955A1

公开(公告)日：2022-05-19

申请号：US17469361

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhun PARK ,  Deokhan BAE ,  Jin-Wook KIM ,  Yuri LEE ,  Inyeal LEE ,  Yoonyoung JUNG

IPC: H01L29/417 ,  H01L27/092 ,  H01L21/8238

Abstract: Disclosed is a semiconductor device including a substrate including first and second active regions, a device isolation layer on the substrate and defining first and second active patterns, first and second gate electrodes running across the first and second active regions and aligned with each other, first and second source/drain patterns on the first and second active patterns, a first active contact connecting the first and second source/drain patterns to each other, and a gate cutting pattern between the first and second gate electrodes. An upper portion of the first active contact includes first and second upper dielectric patterns. The first active contact has a minimum width at a portion between the first and second upper dielectric patterns. A minimum width of the gate cutting pattern is a second width. A ratio of the first width to the second width is in a range of 0.8 to 1.2.

公开(公告)号：US20240096980A1

公开(公告)日：2024-03-21

申请号：US18368725

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inyeal LEE ,  Deokhan BAE ,  Juyoun KIM

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate with first and second regions; first and second source/drain regions on the first and second regions; first and second source/drain contacts on the first and second source/drain regions; and a separation structure intersecting the active pattern between the first and second source/drain contacts, and extending into the active pattern between the first and second source/drain regions, wherein an upper surface of the second source/drain contact is higher than an upper surface of the first source/drain contact, and wherein the separation structure has an asymmetrical structure having an upper surface of a first portion adjacent to the first source/drain contact higher than an upper surface of a second portion adjacent to the second source/drain contact.

公开(公告)号：US20220085011A1

公开(公告)日：2022-03-17

申请号：US17410326

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Jinwook KIM ,  Dongbeen KIM ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM ,  Jongmil YOUN ,  Yonggi JEONG

IPC: H01L27/088 ,  H01L23/50

Abstract: An integrated circuit device includes substrate including a fin-type active area extending on the substrate in a first direction parallel to an upper surface of the substrate, a first gate line crossing the fin-type active area on the substrate and extending in a second direction perpendicular to the first direction, a cut gate line extending in the second direction and being spaced apart from the first gate line with a first gate cut area therebetween, a second gate line extending in the second direction and being spaced apart from the cut gate line with a second gate cut area therebetween, and a power wiring disposed on the cut gate line.