公开(公告)号：US20180005943A1

公开(公告)日：2018-01-04

申请号：US15704049

申请日：2017-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop YOON ,  Kwangsub YOON ,  Jongmil YOUN ,  Hyung Jong LEE

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/485 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L23/5283 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/0653

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

公开(公告)号：US20190027438A1

公开(公告)日：2019-01-24

申请号：US16119475

申请日：2018-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changseop YOON ,  Kwangsub YOON ,  Jongmil YOUN ,  Hyung Jong LEE

IPC: H01L23/528 ,  H01L27/02 ,  H01L23/485 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

公开(公告)号：US20220085011A1

公开(公告)日：2022-03-17

申请号：US17410326

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inyeal LEE ,  Jinwook KIM ,  Dongbeen KIM ,  Deokhan BAE ,  Junghoon SEO ,  Myungyoon UM ,  Jongmil YOUN ,  Yonggi JEONG

IPC: H01L27/088 ,  H01L23/50

Abstract: An integrated circuit device includes substrate including a fin-type active area extending on the substrate in a first direction parallel to an upper surface of the substrate, a first gate line crossing the fin-type active area on the substrate and extending in a second direction perpendicular to the first direction, a cut gate line extending in the second direction and being spaced apart from the first gate line with a first gate cut area therebetween, a second gate line extending in the second direction and being spaced apart from the cut gate line with a second gate cut area therebetween, and a power wiring disposed on the cut gate line.

公开(公告)号：US20190067287A1

公开(公告)日：2019-02-28

申请号：US16176179

申请日：2018-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min YOO ,  Sangyoon KIM ,  Woosik KIM ,  Jongmil YOUN ,  Hwasung RHEE ,  Heedon JEONG

IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.