公开(公告)号：US20230146858A1

公开(公告)日：2023-05-11

申请号：US17964276

申请日：2022-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA ,  Takuya HAGIWARA ,  Takuya MARUYAMA

IPC: H01L29/40 ,  H01L29/739 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L29/7397 ,  H01L21/31116

Abstract: A manufacturing method of a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface and a second main surface, a step of forming a recess in the first main surface and embedding an insulating film in the recess, a step of forming a polysilicon film on the insulating film, a step of forming an interlayer insulating film on the first main surface so as to cover the insulating film and the polysilicon film, and a step of forming a first contact hole and a second contact hole. The semiconductor substrate has a first impurity diffusion region formed in the first main surface, and a second impurity diffusion region in contact with a portion of the first impurity diffusion region, the portion being closer to the second main surface.

公开(公告)号：US20180068845A1

公开(公告)日：2018-03-08

申请号：US15811282

申请日：2017-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya HAGIWARA

IPC: H01L21/027 ,  G03F7/38 ,  G03F7/039 ,  G03F7/32 ,  G03F7/20 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L21/324 ,  H01L21/308 ,  G03F7/16 ,  H01L21/28 ,  H01L21/3105 ,  G03F7/09

CPC classification number: H01L21/0274 ,  G03F7/0392 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2022 ,  G03F7/2028 ,  G03F7/2041 ,  G03F7/32 ,  G03F7/327 ,  G03F7/38 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28017 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/66568

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

公开(公告)号：US20160064403A1

公开(公告)日：2016-03-03

申请号：US14833502

申请日：2015-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya HAGIWARA ,  Tetsuro HANAWA

IPC: H01L27/115 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66568 ,  H01L21/0206 ,  H01L21/0273 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device.In a manufacturing method of a semiconductor device according to an embodiment, when a resist pattern is formed over a cap insulating film comprising a silicon nitride film, the resist pattern is formed through the processes of coating, exposure, and development treatment of a chemical amplification type resist. Then the chemical amplification type resist is applied so as to directly touch the surface of the cap insulating film comprising the silicon nitride film and organic acid pretreatment is applied to the surface of the cap insulating film comprising the silicon nitride film before the coating of the chemical amplification type resist.

Abstract translation: 本发明使得可以提高半导体器件的可靠性。 在根据实施例的半导体器件的制造方法中，当在包括氮化硅膜的帽绝缘膜上形成抗蚀剂图案时，通过化学放大的涂布，曝光和显影处理的过程形成抗蚀剂图案 型抗蚀剂。 然后施加化学放大型抗蚀剂，以便直接接触包含氮化硅膜的帽绝缘膜的表面，并且在涂覆化学品之前将有机酸预处理施加到包含氮化硅膜的帽绝缘膜的表面 放大型抗蚀剂。

公开(公告)号：US20160336173A1

公开(公告)日：2016-11-17

申请号：US15137964

申请日：2016-04-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya HAGIWARA

IPC: H01L21/027 ,  H01L21/324 ,  H01L21/306 ,  G03F7/38 ,  H01L29/66 ,  H01L21/311 ,  G03F7/20 ,  G03F7/32 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/0274 ,  G03F7/0392 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2022 ,  G03F7/2028 ,  G03F7/2041 ,  G03F7/32 ,  G03F7/327 ,  G03F7/38 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28017 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/66568

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Abstract translation: 提高了半导体器件的可靠性。 在制造方法中，在圆形半导体基板上形成被处理膜，在其上形成表面具有防水性的抗蚀剂层。 随后，通过选择性地对半导体衬底的外周区域进行第一晶片边缘曝光，降低圆形半导体衬底的外围区域中的抗蚀剂层的防水性，然后对抗蚀剂进行液浸曝光 层。 随后，对圆形半导体衬底的外围区域进行第二晶片边缘曝光，然后开发已经进行了第一晶片边缘曝光，液浸曝光和第二晶片边缘曝光的抗蚀剂层 ，使得通过使用显影的抗蚀剂层来蚀刻待处理的膜。

公开(公告)号：US20180061664A1

公开(公告)日：2018-03-01

申请号：US15689964

申请日：2017-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu SAITO ,  Takuya HAGIWARA

IPC: H01L21/3213 ,  H01L21/68 ,  H01L21/027 ,  H01L21/47 ,  H01L21/033 ,  H01L21/225

CPC classification number: H01L21/32139 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/2253 ,  H01L21/47 ,  H01L21/682

Abstract: A method of manufacturing a semiconductor device includes forming a reference pattern in an inspection pattern formation region, forming a first mask layer over a semiconductor substrate, while forming a first inspection pattern in the inspection pattern formation region, and measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern. The method further includes implanting ions into the semiconductor substrate using a first mask layer, removing the first mask layer and the first inspection pattern and then forming a second mask layer over the semiconductor substrate, while forming a second inspection pattern in the inspection pattern formation region, and measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern. In plan view, the second inspection pattern is larger than the first inspection pattern and covers the entire region where the first inspection pattern is formed.

公开(公告)号：US20170178897A1

公开(公告)日：2017-06-22

申请号：US15451525

申请日：2017-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya HAGIWARA

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/28 ,  G03F7/32 ,  H01L29/66 ,  G03F7/20 ,  G03F7/09 ,  G03F7/16 ,  G03F7/039 ,  G03F7/38 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/0274 ,  G03F7/0392 ,  G03F7/094 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2022 ,  G03F7/2028 ,  G03F7/2041 ,  G03F7/32 ,  G03F7/327 ,  G03F7/38 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28017 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/66568

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.