公开(公告)号：US20250169137A1

公开(公告)日：2025-05-22

申请号：US18515087

申请日：2023-11-20

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MARUYAMA ,  Toshiya SAITO ,  Takuya MARUYAMA

IPC: H01L29/40

Abstract: A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.

公开(公告)号：US20230146858A1

公开(公告)日：2023-05-11

申请号：US17964276

申请日：2022-10-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro MARUYAMA ,  Takuya HAGIWARA ,  Takuya MARUYAMA

IPC: H01L29/40 ,  H01L29/739 ,  H01L21/311

CPC classification number: H01L29/401 ,  H01L29/7397 ,  H01L21/31116

Abstract: A manufacturing method of a semiconductor device includes a step of preparing a semiconductor substrate having a first main surface and a second main surface, a step of forming a recess in the first main surface and embedding an insulating film in the recess, a step of forming a polysilicon film on the insulating film, a step of forming an interlayer insulating film on the first main surface so as to cover the insulating film and the polysilicon film, and a step of forming a first contact hole and a second contact hole. The semiconductor substrate has a first impurity diffusion region formed in the first main surface, and a second impurity diffusion region in contact with a portion of the first impurity diffusion region, the portion being closer to the second main surface.

公开(公告)号：US20160064323A1

公开(公告)日：2016-03-03

申请号：US14835284

申请日：2015-08-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroaki SEKIKAWA ,  Hidenori SATO ,  Yotaro GOTO ,  Takuya MARUYAMA ,  Masaaki SHINOHARA

IPC: H01L23/528 ,  H01L27/146 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/31051 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L22/30 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/14603 ,  H01L27/14687 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.

Abstract translation: 连接部分将铜基第一布线层与布置在第一扩散阻挡膜的上侧上的铜基第二布线层连接。 第一扩散阻挡膜包括在二维视图中形成在作为二维视图的局部区域的半导体电路区域中形成的第一开口区域和形成为与二维视图中的第一开口区域不同的开口区域的第二开口区域。 开口区域形成在与形成为允许连接部分穿过第一扩散阻挡膜的开口区域不同的区域中。 标记布线层设置在与第二布线层相同的层的正上方的第二开口区域的正上方。 第二扩散阻挡膜布置成与标记布线层的上表面接触。

公开(公告)号：US20210118897A1

公开(公告)日：2021-04-22

申请号：US17032839

申请日：2020-09-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takuya MARUYAMA ,  Takahiro MARUYAMA

IPC: H01L27/11568 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

Abstract: A manufacturing method of a semiconductor device includes: (a) forming a gate structure for a control gate electrode on a semiconductor substrate; (b) forming a charge storage film so as to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the conductive film such that the charge storage film and the conductive film remain in this order on the first side surface and the second side surface of the gate structure, thereby forming the memory gate electrode; and (e) removing apart of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure.