公开(公告)号：US20210313326A1

公开(公告)日：2021-10-07

申请号：US16840964

申请日：2020-04-06

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Ye LU ,  Lixin GE

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Certain aspects of the present disclosure generally relate to transistors in a layered arrangement. An example semiconductor device generally includes a substrate, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor is disposed above the substrate and is a gate-all-around (GAA) field-effect transistor (FET). The PMOS transistor is disposed above the substrate, is a fin field-effect transistor (finFET), and is in a layered arrangement with the NMOS transistor.

公开(公告)号：US20210280684A1

公开(公告)日：2021-09-09

申请号：US16812292

申请日：2020-03-07

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Haining YANG ,  Junjing BAO

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L29/66

Abstract: A gate all around transistor may be improved to provide better transistor circuits performance. In one example, a transistor circuit may include a dielectric or air gap as an insulator between the channels of the transistors in the circuit. In another example, a transistor may include a first channel surrounded by a first metal, a second channel surrounded by a second metal proximate to the first channel, and an insulator, such as a dielectric or air gap, between the first metal and the second metal. The insulator helps reduce the parasitic capacitance between the source/drain regions and the metal fill regions of the transistor.

公开(公告)号：US20210233911A1

公开(公告)日：2021-07-29

申请号：US16774278

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Ye LU ,  Junjing BAO ,  Chenjie TANG

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

公开(公告)号：US20210089865A1

公开(公告)日：2021-03-25

申请号：US16576597

申请日：2019-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Ye LU

IPC: G06N3/04 ,  G06F7/544 ,  G06F17/15

Abstract: An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

公开(公告)号：US20200007105A1

公开(公告)日：2020-01-02

申请号：US16023186

申请日：2018-06-29

Applicant: QUALCOMM Incorporated

Inventor： Chao SONG ,  Haitao CHENG ,  Ye LU ,  Dongjiang QIAO

IPC: H03H7/30 ,  H03H1/02 ,  H03H3/00 ,  H03H7/06 ,  H01L49/02 ,  H01L23/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit (IC) device includes a first resistive strip having an input terminal and an output terminal. The IC device further includes a second resistive strip having a terminal coupled to a voltage. The second resistive strip may be coplanar with the first resistive strip. The IC device further includes a capacitor formed by the first resistive strip and the second resistive strip.

公开(公告)号：US20190115342A1

公开(公告)日：2019-04-18

申请号：US15862533

申请日：2018-01-04

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE

IPC: H01L27/08 ,  H01L29/94 ,  H01L29/66 ,  H01L21/822 ,  H01L21/66 ,  H01L29/06 ,  H01L27/02

Abstract: A FinMosVar (fin metal oxide semiconductor (MOS) varactor) has an improved number of fins. The number of fins are determined based on a measured or calculated gate resistance of the FinMosVar and a measured or calculated capacitance of the FinMosVar. The number of fins is less than twenty (20) fins. The FinMosVar also includes a source region, a drain region and a channel region. The drain region has a same type of doping as the source region. The channel region has the same type of doping as the source region.

公开(公告)号：US20190103459A1

公开(公告)日：2019-04-04

申请号：US15724147

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG

IPC: H01L49/02 ,  H01L21/321 ,  H01L21/768 ,  H01L27/11502 ,  H01L29/66 ,  H01L27/108

Abstract: A capacitor may include a first conductive layer forming a first capacitor plate, a second conductive layer forming a second capacitor plate, and a first insulating material on the first conductive layer. The first insulating material may include a positive capacitance material. The capacitor may further include a second insulating material disposed over the first insulating material and between the first insulating material and the second conductive layer. The second insulating material may include a negative capacitance ferroelectric material.

公开(公告)号：US20210233909A1

公开(公告)日：2021-07-29

申请号：US16751371

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG ,  Xiaochun ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. One example GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20210124793A1

公开(公告)日：2021-04-29

申请号：US16666699

申请日：2019-10-29

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Ye LU ,  Yandong GAO ,  Xiaochun ZHU ,  Xia LI

IPC: G06F17/16 ,  G06N3/063 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

公开(公告)号：US20210005604A1

公开(公告)日：2021-01-07

申请号：US16918770

申请日：2020-07-01

Applicant: Qualcomm Incorporated

Inventor： Lixin GE ,  Ye LU ,  John Jianhong ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/033 ,  H01L29/66

Abstract: Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel and a first set of work function layer. The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel and a second set of work function layer. The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.