公开(公告)号：US20250132262A1

公开(公告)日：2025-04-24

申请号：US18649229

申请日：2024-04-29

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Hong Bok WE ,  Zhijie WANG ,  Sang-Jae LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10

Abstract: A device includes a substrate that includes a first layer stack including metal and dielectric layers. A first metal layer includes first contacts disposed in a first region and to electrically connect to an IC device, via pads disposed in a second region offset along a first direction, and traces electrically connecting the first contacts and the via pads. The substrate includes, in both regions, a solder resist layer disposed on the first metal layer and a first dielectric layer. The solder resist layer defines openings to the first contacts and the via pads. The substrate includes a second layer stack disposed on the second region and including a second metal layer on the solder resist layer opposite the first layer stack. The second metal layer defines second contacts to electrically connect to second IC device(s) and includes conductive vias between the via pads and the second contacts.

公开(公告)号：US20250098066A1

公开(公告)日：2025-03-20

申请号：US18470148

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Sang-Jae LEE ,  Zhijie WANG

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A substrate comprising a core layer, at least one first dielectric layer coupled to a first surface of the core layer, at least one second dielectric layer coupled to a second surface of the core layer, a plurality of interconnects located at least partially in the at least one first dielectric layer; a region comprising a plurality of block interconnects of an interconnect block; and a solder resist layer coupled to the at least one first dielectric layer.

公开(公告)号：US20240321752A1

公开(公告)日：2024-09-26

申请号：US18190019

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Sang-Jae LEE ,  Zhijie WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L25/165 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15174

Abstract: A package comprising a substrate and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first plurality of interconnects, and a first integrated device located at least partially in the substrate. The first integrated device is coupled to the first plurality of interconnects through a first plurality of solder interconnects. The second integrated device is coupled to the first plurality of interconnects through a second plurality of solder interconnects.

公开(公告)号：US20240194545A1

公开(公告)日：2024-06-13

申请号：US18063384

申请日：2022-12-08

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Sang-Jae LEE ,  Zhijie WANG

IPC: H01L23/06 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/06 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/19 ,  H01L2224/24011 ,  H01L2224/244

Abstract: Disclosed are examples of die packages that incorporate metal frames with metal pockets. One or more dies may be placed within the metal pockets. Due to the structural integrity provided by the metal frame, warpage is reduced or eliminated. As a result, die packages with thin dies may be fabricated. Further, due to the electrical conductivity provided by the metal frame, the metal frame may be used as an electrical shield to protect the dies.

公开(公告)号：US20250046688A1

公开(公告)日：2025-02-06

申请号：US18363557

申请日：2023-08-01

Applicant: QUALCOMM Incorporated

Inventor： Zhijie WANG ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Sang-Jae LEE ,  Seongho KIM

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

Abstract: An integrated device includes a die including active circuitry and a first set of contacts; a first substrate including a second set of contacts and a third set of contacts on a first side of the first substrate and a fourth set of contacts on a second side of the first substrate; a mold compound disposed on the first side of the first substrate and at least partially encapsulating the die; and a set of through mold conductors coupled to the third set of contacts and extending through the mold compound, wherein an upper surface of the mold compound, an upper surface of the die, and an upper surface of each of the set of through mold conductors are coplanar.

公开(公告)号：US20250096051A1

公开(公告)日：2025-03-20

申请号：US18471069

申请日：2023-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Kun FANG ,  Suhyung HWANG ,  Sang-Jae LEE ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Zhijie WANG ,  Seongho KIM

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/16

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.

公开(公告)号：US20250062246A1

公开(公告)日：2025-02-20

申请号：US18450943

申请日：2023-08-16

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Hong Bok WE ,  Sang-Jae LEE

IPC: H01L23/00 ,  H01L23/498

Abstract: Disclosed are devices in which a die, such as a system-on-chip (SoC) die is attached to an interposer with a mold. Unlike convention devices, the contact area for adhesion is increased by providing vertical surfaces in addition to lateral surfaces for attachment. In so doing, possibility of delamination is decreased significantly.

公开(公告)号：US20240274516A1

公开(公告)日：2024-08-15

申请号：US18168420

申请日：2023-02-13

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG ,  Hong Bok WE ,  Sang-Jae LEE

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/373

CPC classification number: H01L23/49816 ,  H01L23/293 ,  H01L23/3737

Abstract: Disclosed are apparatuses and methods for fabricating the apparatuses. In an aspect, an apparatus may include: an interposer including a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically couple the first metal layer and the second metal layer, and a plurality of solder resist posts disposed on a bottom surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, where the TIM is configured to thermally coupled the die and the bottom surface portion of the second metal layer.

公开(公告)号：US20230352390A1

公开(公告)日：2023-11-02

申请号：US17735075

申请日：2022-05-02

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Joan Rey Villarba BUOT ,  Zhijie WANG ,  Marcus HSU ,  Sang-Jae LEE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L24/32 ,  H01L2224/32237 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L23/49822

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.