公开(公告)号：US20220093594A1

公开(公告)日：2022-03-24

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Deepak SHARMA ,  Bharani CHAVA ,  Hyeokjin LIM ,  Peijie FENG ,  Seung Hyuk KANG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Kern RIM ,  Giridhar NALLAPATI ,  Venugopal BOYNAPALLI ,  Foua VANG

IPC: H01L27/095 ,  H03K19/0185 ,  H01L23/528 ,  H01L29/78

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US20210351276A1

公开(公告)日：2021-11-11

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20240421209A1

公开(公告)日：2024-12-19

申请号：US18334226

申请日：2023-06-13

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Peijie FENG

IPC: H01L29/51 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: Disclosed are semiconductor devices and fabrication methods. A semiconductor device includes a first gate structure including a first set of channels disposed along a first direction through a first gate metal, and a first set of gate dielectrics disposed between the first set of channels and the first gate metal. The first set of gate dielectrics each have a first thickness. The semiconductor device further includes a second gate structure including a second set of channels disposed along the first direction through a second gate metal, and a second set of gate dielectrics disposed between the second set of channels and the second gate metal. The second set of gate dielectrics each have a second thickness. The second thickness is greater than the first thickness and the second set of channels is less in number than the first set of channels.

公开(公告)号：US20210233911A1

公开(公告)日：2021-07-29

申请号：US16774278

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Peijie FENG ,  Ye LU ,  Junjing BAO ,  Chenjie TANG

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

Abstract: Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.

公开(公告)号：US20250096075A1

公开(公告)日：2025-03-20

申请号：US18469501

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Yandong GAO ,  Peijie FENG

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

Abstract: In an aspect, a semiconductor memory cell comprises gate structures separated by source or drain (S/D) structures, a frontside (FS) inter-layer dielectric (FS-ILD) layer above the gate and S/D structures, FS metal zero (FM0) interconnects above the FS-ILD layer, a backside (BS) inter-layer dielectric (BS-ILD) layer below the gate and S/D structures, BS metal zero (BM0) interconnects below the BS-ILD layer, at least one FS source drain contact (FSDC) electrically connecting an FM0 interconnect to a top surface of an S/D structure, and at least one BS S/D contact (BSDC) electrically connecting a BMO interconnect to a bottom surface of an S/D structure. The semiconductor memory cell comprises NFETs and PFETs to form a cross-coupled inverter pair. For each inverter in the pair, one of VDD and VSS are provided by an FSDC and the other of VDD and VSS is provided by a BSDC.

公开(公告)号：US20210233909A1

公开(公告)日：2021-07-29

申请号：US16751371

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG ,  Xiaochun ZHU

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. One example GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material.

公开(公告)号：US20240429236A1

公开(公告)日：2024-12-26

申请号：US18339715

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Peijie FENG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Disclosed are gate-all-around (GAA) devices formed on a nanosheet wafer that includes multiple nanosheet (NS) structures including first and second NS structures. The first NS structure may include N nanosheets, where N≥2. All N nanosheets may function as channels in the first NS structure. The second NS structure may include one or more nanosheets in which N−M of them function as channels, where 1≤M

公开(公告)号：US20210305155A1

公开(公告)日：2021-09-30

申请号：US16834618

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Giridhar NALLAPATI ,  Peijie FENG

IPC: H01L23/522 ,  H01L21/768

Abstract: An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero.

公开(公告)号：US20210057410A1

公开(公告)日：2021-02-25

申请号：US16817446

申请日：2020-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Hyunwoo PARK ,  Peijie FENG

IPC: H01L27/092 ,  H01L29/06

Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

公开(公告)号：US20200234999A1

公开(公告)日：2020-07-23

申请号：US16250098

申请日：2019-01-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Peijie FENG ,  Chenjie TANG

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238

Abstract: Certain aspects of the present disclosure provide a transistor device, such as a fin field-effect transistor (finFET) device, and techniques for fabrication thereof. One example transistor device generally includes one or more semiconductor channel regions and a metal region disposed above the one or more semiconductor channel regions. The metal region has one or more gaps (e.g., air gaps) disposed therein.