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公开(公告)号：US11900111B2
公开(公告)日：2024-02-13
申请号：US17448816
申请日：2021-09-24
Applicant: QUALCOMM Incorporated
Inventor： Srijesh Sudarsanan , Deepak Mathew , Marc Hoffman , Gerald Sweeney , Sundar Rajan Balasubramanian , Hongfeng Dong , Yurong Sun , Seyedmehdi Sadeghzadeh
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30101
Abstract: A device includes a vector register file, a memory, and a processor. The vector register file includes a plurality of vector registers. The memory is configured to store a permutation instruction. The processor is configured to access a periodicity parameter of the permutation instruction. The periodicity parameter indicates a count of a plurality of data sources that contain source data for the permutation instruction. The processor is also configured to execute the permutation instruction to, for each particular element of multiple elements of a first permutation result register of the plurality of vector registers, select a data source of the plurality of data sources based at least in part on the count of the plurality of data sources and populate the particular element based on a value in a corresponding element of the selected data source.
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公开(公告)号：US20140281368A1
公开(公告)日：2014-09-18
申请号：US13829503
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Ajay Anant Ingle , Lucian Codrescu , David J. Hoyle , Jose Fridman , Marc M. Hoffman , Deepak Mathew
IPC: G06F9/30
CPC classification number: G06F9/3853
Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.
Abstract translation: 用于在一个或多个时隙中执行多个指令的示例性方法包括接收包括多个指令的分组，并以时间共享的方式在一个或多个时隙中执行多个指令。 每个时隙与执行数据路径或存储器数据路径相关联。 用于执行多个阶段中的至少一个指令的示例性方法包括：接收包括指令的分组，将指令分解成多个阶段，以及执行多个阶段中的指令。
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公开(公告)号：US12159140B2
公开(公告)日：2024-12-03
申请号：US17732361
申请日：2022-04-28
Applicant: QUALCOMM Incorporated
Inventor： Srijesh Sudarsanan , Deepak Mathew , Marc Hoffman , Sundar Rajan Balasubramanian , Mansi Jain , James Lee , Gerald Sweeney
Abstract: An electronic device receives a single instruction to apply a neural network operation to a set of M-bit elements stored in one or more input vector registers to initiate a sequence of computational operations related to a neural network. In response to the single instruction, the electronic device implements the neural network operation on the set of M-bit elements to generate a set of P-bit elements by obtaining the set of M-bit elements from the one or more input vector registers, quantizing each of the set of M-bit elements from M bits to P bits, and packing the set of P-bit elements into an output vector register. P is smaller than M. In some embodiments, the neural network operation is a quantization operation including at least a multiplication with a quantization factor and an addition with a zero point.
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公开(公告)号：US20230097103A1
公开(公告)日：2023-03-30
申请号：US17448810
申请日：2021-09-24
Applicant: QUALCOMM Incorporated
Inventor： Santosh Srivatsan Srinivasan , Marc Hoffman , Srijesh Sudarsanan , Deepak Mathew , Hongfeng Dong , Gerald Sweeney
Abstract: A device includes a memory configured to store a fast Fourier transform (FFT) instruction and parameters of the FFT instruction, a read-only memory including a phasor table, and a processor. The processor is configured to execute the FFT instruction to determine, based on the parameters of the FFT instruction, a start value and a step size. The processor is configured to execute the FFT instruction to access the phasor table according to the start value and the step size to obtain a set of twiddle values. The processor is also configured to execute the FFT instruction to compute, for each pair of input values in a set of input data, an output value based on the pair of input values and a twiddle value, of the set of twiddle values, that corresponds to that pair of input values.
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公开(公告)号：US20140270017A1
公开(公告)日：2014-09-18
申请号：US13842663
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
Inventor： Deepak Mathew , Ajay Anant Ingle , Mao Zeng , Marc M. Hoffman
IPC: H04L25/02
CPC classification number: H04L25/0212 , H04B1/70752 , H04B1/7093 , H04B2201/70707
Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.
Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。
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Patent Agency Ranking
公开(公告)号：US09130786B2
公开(公告)日：2015-09-08
申请号：US13842663
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Deepak Mathew , Ajay Anant Ingle , Mao Zeng , Marc M. Hoffman
IPC: H04B1/00 , H04L27/00 , H04L25/02 , H04B1/7075 , H04B1/7093
CPC classification number: H04L25/0212 , H04B1/70752 , H04B1/7093 , H04B2201/70707
Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.
Abstract translation: 一种装置包括选择逻辑，其被配置为选择存储在第一组寄存器中的第一组采样的第一子集。 第一子集包括存储在第一组寄存器的第一寄存器中的第一样本，并且还包括存储在第一组寄存器的第二寄存器上的第二样本。 该装置还包括移位逻辑，配置成移位存储在第二组寄存器中的第二组采样。 该装置还包括信道估计器，其被配置为基于第一子集生成与信道估计相关联的第一值，并且还基于所移位的第二组样本的第二子集。
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公开(公告)号：US20150052330A1
公开(公告)日：2015-02-19
申请号：US13967191
申请日：2013-08-14
Applicant: QUALCOMM Incorporated
Inventor： Ajay Anant Ingle , Marc Murray Hoffman , Deepak Mathew , Mao Zeng
IPC: G06F9/30
CPC classification number: G06F9/3001 , G06F9/30036 , G06F9/3887 , G06F9/3897
Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.
Abstract translation: 在特定实施例中，一种方法包括在处理器处执行向量指令。 矢量指令包括包括多个元素的矢量输入。 执行向量指令包括提供多个元素中的第一元素作为第一输出。 执行向量指令还包括对第一元素和多个元素的第二元素执行算术运算以提供第二输出。 执行向量指令还包括将第一输出和第二输出存储在输出向量中。
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公开(公告)号：US20170094545A1
公开(公告)日：2017-03-30
申请号：US15234634
申请日：2016-08-11
Applicant: QUALCOMM Incorporated
Inventor： Parvathanathan Subrahmanya , Qiang Shen , Aamod Dinkar Khandekar , Mariam Motamed , Wanshi Chen , Hanfang Pan , Deepak Mathew
CPC classification number: H04W24/10 , H04L1/0026 , H04L1/0027 , H04L1/0029 , H04L5/001 , H04L5/0048 , H04L5/0057 , H04W8/22
Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity. The UE may then prioritize the channel state processes and/or may transmit one or more non-current reports.
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公开(公告)号：US09363749B2
公开(公告)日：2016-06-07
申请号：US13968153
申请日：2013-08-15
Applicant: QUALCOMM Incorporated
Inventor： Deepak Mathew , Garret Webster Shih , Jose Fridman , Robin Lee Brown
CPC classification number: H04W52/02 , H04W52/0245 , H04W52/028 , H04W52/0287 , Y02D70/00 , Y02D70/1222 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/146
Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).
Abstract translation: 系统和方法基于信道状态和/或数据速率来动态地缩放由电子设备的电路消耗的功率。 电子设备然后根据功率缩放来操作。 缩放可以根据有效数据速率，多输入多输出（MIMO）层，接收器类型，单元方案或多个载波来实现。 可以基于信道条件或信道质量指数（CQI）中的至少一个来预测多个MIMO层。
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公开(公告)号：US10466967B2
公开(公告)日：2019-11-05
申请号：US15224237
申请日：2016-07-29
Applicant: QUALCOMM Incorporated
Inventor： Deepak Mathew , Ajay Anant Ingle , Yurong Sun , Jianming Zhu , Marc Hoffman
Abstract: An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.
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