公开(公告)号：US11676922B2

公开(公告)日：2023-06-13

申请号：US16665883

申请日：2019-10-28

Applicant: QUALCOMM Incorporated

Inventor： Li-Sheng Weng ,  Yue Li ,  Yangyang Sun

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/10122 ,  H01L2224/1182 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/14133 ,  H01L2924/3025

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

公开(公告)号：US10321575B2

公开(公告)日：2019-06-11

申请号：US14842403

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane ,  Ruey Kae Zang

IPC: H05K1/18 ,  H01L21/56 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H01L23/64 ,  H01L21/48 ,  H01L23/13 ,  H01L23/16

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

公开(公告)号：US20160020759A1

公开(公告)日：2016-01-21

申请号：US14335681

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K5/15 ,  H01L23/538

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。

公开(公告)号：US09654090B2

公开(公告)日：2017-05-16

申请号：US15138142

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

公开(公告)号：US20170125152A1

公开(公告)日：2017-05-04

申请号：US14931659

申请日：2015-11-03

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F27/28 ,  H01F41/04 ,  H05K1/18 ,  H01F27/29

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/02 ,  H01F27/29 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/18

Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

公开(公告)号：US09041176B2

公开(公告)日：2015-05-26

申请号：US13764356

申请日：2013-02-11

Applicant: Qualcomm Incorporated

Inventor： Yue Li ,  Charles D. Paynter ,  Ruey Kae Zang

IPC: H01L23/02 ,  H01L21/00 ,  H01L21/82 ,  H01L49/02 ,  H01L25/065

CPC classification number: H01L21/82 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/00 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19105 ,  Y10T29/53174

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract translation: 一些实施方案提供了包括第一封装衬底，第一部件，第二封装衬底，第二部件和第三部件的结构。 第一封装衬底具有第一区域。 第一部件具有第一高度并且位于第一区域上。 第二封装衬底耦合到第一封装衬底。 第二封装衬底具有第二和第三区域。 第二封装衬底的第二区域垂直地与第一封装衬底的第一区域重叠。第二封装衬底的第三区域与第一封装衬底的第一区域不重叠。 第二部件具有第二高度并且位于第二区域上。 第三个组件位于第三个区域。 第三部件具有大于第一和第二高度中的每一个的第三高度。

公开(公告)号：US20140097512A1

公开(公告)日：2014-04-10

申请号：US13764356

申请日：2013-02-11

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Charles D. Paynter ,  Ruey Kae Zang

IPC: H01L21/82

CPC classification number: H01L21/82 ,  H01L25/065 ,  H01L25/0657 ,  H01L28/00 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19105 ,  Y10T29/53174

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract translation: 一些实施方案提供了包括第一封装衬底，第一部件，第二封装衬底，第二部件和第三部件的结构。 第一封装衬底具有第一区域。 第一部件具有第一高度并且位于第一区域上。 第二封装衬底耦合到第一封装衬底。 第二封装衬底具有第二和第三区域。 第二封装衬底的第二区域垂直地与第一封装衬底的第一区域重叠。第二封装衬底的第三区域与第一封装衬底的第一区域不重叠。 第二部件具有第二高度并且位于第二区域上。 第三个组件位于第三个区域。 第三部件具有大于第一和第二高度中的每一个的第三高度。

公开(公告)号：US12062648B2

公开(公告)日：2024-08-13

申请号：US17484475

申请日：2021-09-24

Applicant: QUALCOMM Incorporated

Inventor： Darko Popovic ,  Durodami Lisk ,  Yue Li

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16225

Abstract: Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

公开(公告)号：US20230090181A1

公开(公告)日：2023-03-23

申请号：US17483325

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Yue Li ,  Durodami Lisk ,  Jinying Sun

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor die (“die”) employing repurposed seed layer for forming additional signal paths to a back end-of-line (BEOL) structure of the die, and related integrated circuit (IC) packages and fabrication methods. A seed layer is repurposed that was disposed adjacent the BEOL interconnect structure to couple an under bump metallization (UBM) interconnect without a coupled interconnect bump thus forming an unraised interconnect bump, to a UBM interconnect that has a raised interconnect bump. To couple the unraised interconnect bump to the raised interconnect bump, the seed layer is selectively removed during fabrication to leave a portion of the seed layer repurposed that couples the UBM interconnect that does not have an interconnect bump to the UBM interconnect that has a raised interconnect bump. Additional routing paths can be provided between raised interconnect bumps to the BEOL interconnect structure through coupling of UBM interconnects to an unraised interconnect bump.

公开(公告)号：US10231324B2

公开(公告)日：2019-03-12

申请号：US14264836

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Ryan David Lane ,  Yue Li ,  Charles David Paynter ,  Ruey Kae Zang

IPC: H01L21/48 ,  H05K1/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/528 ,  H01L23/522 ,  H01L23/525

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.