公开(公告)号：US10114074B2

公开(公告)日：2018-10-30

申请号：US15955013

申请日：2018-04-17

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  Luverne Ray Peterson

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

公开(公告)号：US09654090B2

公开(公告)日：2017-05-16

申请号：US15138142

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

公开(公告)号：US09111848B1

公开(公告)日：2015-08-18

申请号：US14272324

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Dubowski ,  Thomas Clark Bryan ,  Mark Wayland

IPC: H01L23/58 ,  H01L21/66 ,  H01L27/118 ,  G01R31/28 ,  G01R31/3185

CPC classification number: H01L22/20 ,  G01R31/2884 ,  G01R31/31701 ,  G01R31/31724 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318555 ,  H01L27/11807

Abstract: A control circuit generates data signals and configuration commands that are provided to an interface circuit. The interface circuit includes a configuration circuit that generates configuration signals according to the configuration commands and a drive component that generates interface signals according to the data signals. The interface signals are generated with a drive characteristic determined according to the configuration signals applied to configuration devices that selectively activate a configuration of drive devices. A diagnostic circuit is coupled to the control circuit and the interface circuit and is configured to receive a test state indication and acquire a corresponding portion of the configuration signals. The diagnostic circuit compares the test state indication and the portion of the configuration signals to diagnose a stuck-at fault condition within a faulty configuration circuit and propagate a fault indication to the control circuit.

Abstract translation: 控制电路产生提供给接口电路的数据信号和配置命令。 接口电路包括根据配置命令产生配置信号的配置电路和根据数据信号产生接口信号的驱动组件。 通过根据施加到选择性地激活驱动装置的配置的配置装置的配置信号确定的驱动特性来生成接口信号。 诊断电路耦合到控制电路和接口电路，并且被配置为接收测试状态指示并获取配置信号的相应部分。 诊断电路比较测试状态指示和配置信号的部分，以诊断故障配置电路内的故障状态，并将故障指示传播到控制电路。

公开(公告)号：US20160294383A1

公开(公告)日：2016-10-06

申请号：US14792441

申请日：2015-07-06

Applicant: QUALCOMM, Incorporated

Inventor： Mohammed Mizanur Rahman ,  Jacob Stephen Schneider ,  Thomas Clark Bryan ,  LuVerne Ray Peterson ,  Gregory Francis Lynch ,  Alvin Leng Sun Loke

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03F3/45197 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45504 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03878

Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Abstract translation: 提供了可编程均衡器和相关方法。 均衡器包括分别与第一电压轨（Vdd）和第二电压轨（地）之间的一对输入FET和一对负载电阻串联耦合的一对电流设定场效应晶体管（FET）。 可编程均衡电路耦合在输入FET的源极之间，包括多个可选择的电阻路径和可变电容器，其也可以被配置为多个可选择的电容路径。 每个可选择的电阻路径（以及每个可选择的电容路径）包括用于选择性地耦合在输入FET的源极之间的对应的电阻（或电容）路径的选择FET。 在其中一个输入FET被参考栅极电压偏置的情况下，每个选择FET的源极耦合到这种输入FET的源极。

公开(公告)号：US09350339B2

公开(公告)日：2016-05-24

申请号：US14335681

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Stephen Knol ,  Gregory Francis Lynch ,  Tin Tin Wee ,  LuVerne Ray Peterson ,  Yue Li

IPC: H03K3/00 ,  H03K5/15 ,  H01L23/538 ,  G06F1/10 ,  G11C7/22 ,  H01L25/065

CPC classification number: H03K5/15013 ,  G06F1/10 ,  G11C7/22 ,  H01L23/5384 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。

公开(公告)号：US20160094202A1

公开(公告)日：2016-03-31

申请号：US14503090

申请日：2014-09-30

Applicant: QUALCOMM Incorporated

Inventor： Timothy Mowry Hollis ,  Thomas Clark Bryan ,  Mark Wayland

IPC: H03K3/011 ,  G11C11/4096

CPC classification number: H03K3/011 ,  G11C11/4096 ,  H03K19/0005 ,  H03K19/00384 ,  H03K19/018585

Abstract: Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed. Settings that result from the calibration are referred to as calibration codes. The output driver circuit includes multiple pull-up elements that are enabled or disabled to produce a desired output impedance when the output is high and multiple pull-down elements that are enabled or disabled to produce the desired output impedance when the output is low. The number of pull-up elements that are enabled and the number of pull-down elements that are enabled is set by calibration. The results of the calibration (i.e., the number of enabled elements for the pull-up and the number of enabled elements for the pull-down) are used to set controls for an amount of pre-emphasis and/or to set controls for output slew rates.

Abstract translation: 公开了基于来自校准驱动电路的输出阻抗的信息来均衡输出驱动器电路的系统和方法。 由校准产生的设置称为校准代码。 输出驱动器电路包括多个上拉元件，其在输出为高电平时使能或禁止产生期望的输出阻抗，并且当输出为低电平时启用或禁用以产生所需输出阻抗的多个下拉元件。 启用的上拉元件数量和启用的下拉元件数量通过校准设置。 校准的结果（即，上拉的使能元件数量和下拉使能元件的数量）用于设置预加重量的控制和/或设置控制输出 压摆率。

公开(公告)号：US09245870B1

公开(公告)日：2016-01-26

申请号：US14516763

申请日：2014-10-17

Applicant: QUALCOMM Incorporated

Inventor： LuVerne Ray Peterson ,  Thomas Clark Bryan ,  Alvin Leng Sun Loke ,  Tin Tin Wee ,  Gregory Francis Lynch ,  Stephen Robert Knol

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/065 ,  G06F1/10 ,  G06F17/5072 ,  G06F2217/62 ,  G06F2217/78 ,  H01L2924/0002 ,  H04L7/0095 ,  H01L2924/00

Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

Abstract translation: 电路包括具有暴露的数据节点的第一阵列的第一管芯和具有暴露的数据节点的第二阵列的第二管芯，其中第一阵列的给定数据节点对应于第二阵列上的相应的数据节点，此外， 所述第一阵列和所述第二阵列共享所述数据节点的空间布置，其中所述第一裸片具有用于所述第一阵列的第一侧上的所述第一阵列的每个数据节点的数据输入和顺序逻辑电路，并且其中所述第二阵列 管芯具有用于第二阵列的第二侧上的第二阵列的每个数据节点的数据输出和顺序逻辑电路，第一和第二侧是不同的。

公开(公告)号：US10429441B2

公开(公告)日：2019-10-01

申请号：US15603779

申请日：2017-05-24

Applicant: QUALCOMM Incorporated

Inventor： Tapan Jyoti Chakraborty ,  Alvin Leng Sun Loke ,  Hong Dai ,  Thomas Clark Bryan

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

公开(公告)号：US09977078B2

公开(公告)日：2018-05-22

申请号：US14339224

申请日：2014-07-23

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  LuVerne Ray Peterson

IPC: G06F17/50 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31716 ,  G01R31/318513

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

公开(公告)号：US20160025807A1

公开(公告)日：2016-01-28

申请号：US14339224

申请日：2014-07-23

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  LuVerne Ray Peterson

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31716 ,  G01R31/318513

Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Abstract translation: 提供了用于环回测试的电路和方法。 一个管芯将每个发射器（TX）的接收器（RX）以及每个接收器的TX都包含在内。 该架构被应用于每个位，因此，例如，在操作期间发送或接收32个数据位的管芯将具有32个收发器（每个位一个）。 专注于收发器之一，环回架构包括TX数据路径和RX数据路径，其通过诸如收发器之间的通孔的外部接点相互耦合。 芯片还包括馈送TX数据路径的发射时钟树和馈送RX数据路径的接收时钟树。 传输时钟树通过露出在芯片表面上的导电时钟节点馈送接收时钟树。 一些系统还包括时钟路径中的可变延迟。