公开(公告)号：US20250118645A1

公开(公告)日：2025-04-10

申请号：US18987457

申请日：2024-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H10D1/68

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US09269492B2

公开(公告)日：2016-02-23

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Pr Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/38 ,  H01G4/005 ,  H01L49/02 ,  H01G4/33 ,  H01G4/10

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US20140231957A1

公开(公告)日：2014-08-21

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  PR Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L23/538 ,  H01L27/08

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上互连层的至少一部分的第一电容器板和具有MIM电容层的至少一部分的第二电容器板。

公开(公告)号：US20140092523A1

公开(公告)日：2014-04-03

申请号：US13799079

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Lixin Ge ,  Bin Yang ,  Jihong Choi

IPC: H01G4/012 ,  H01G4/005 ,  H01G4/38

CPC classification number: H01G4/012 ,  H01G4/005 ,  H01G4/10 ,  H01G4/33 ,  H01G4/38 ,  H01L28/86

Abstract: An orthogonal finger capacitor includes a layer having an anode bone frame adjacent a cathode bone frame, the anode bone frame having a first portion extending along an axis and a second portion extending perpendicular to the axis. A set of anode fingers extends from the first portion. A set of cathode fingers extends from the cathode bone frame, interdigitated with the set of anode fingers. An overlaying layer has another anode bone frame having a first portion parallel to the axis and a perpendicular second portion. A via couples the overlaying anode bone frame to the underlying anode bone frame. The via is located where the first portion of the overlaying anode bone frame overlaps the second portion of the underlying anode bone frame or, optionally, where the second portion of the overlying anode bone frame overlaps the first portion of the underlying anode bone frame.

Abstract translation: 正交手指电容器包括具有邻近阴极骨架的阳极骨架的层，阳极骨架具有沿轴线延伸的第一部分和垂直于轴线延伸的第二部分。 一组阳极指从第一部分延伸。 一组阴极指状物从阴极骨框架延伸，与一组阳极指状物交叉。 覆盖层具有另一阳极骨架，其具有平行于轴线的第一部分和垂直的第二部分。 A通孔将覆盖的阳极骨框架耦合到下面的阳极骨框架。 通孔位于覆盖阳极骨框架的第一部分与下面的阳极骨框架的第二部分重叠的位置，或者可选地，其中上覆的阳极骨架的第二部分与下面的阳极骨架的第一部分重叠。

公开(公告)号：US10833017B2

公开(公告)日：2020-11-10

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang Liu ,  Haining Yang ,  Youseok Suh ,  Jihong Choi ,  Junjing Bao

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

公开(公告)号：US20140197520A1

公开(公告)日：2014-07-17

申请号：US13743434

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  Bin Yang ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L28/24

Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.

Abstract translation: 在特定实施例中，一种方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露光学平坦化层的区域。 至少部分地在该区域内形成电阻层。 该方法还包括去除光学平坦化层的至少第二部分和电阻层的至少第三部分以形成电阻器。

公开(公告)号：US20240079352A1

公开(公告)日：2024-03-07

申请号：US17929408

申请日：2022-09-02

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  Lily Zhao ,  Dongming He

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/642 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16235 ,  H01L2224/17163 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19041 ,  H01L2924/30101 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned. In this manner, the capacitor interposer substrate can maintain interconnect compatibility to the die(s) and package substrate if the die(s) and package substrate have a pattern of die interconnects and external interconnects that are designed to align with each other when coupled to each other.

公开(公告)号：US20220375851A1

公开(公告)日：2022-11-24

申请号：US17324614

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Stanley Seungchul Song ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L49/02

Abstract: Deep trench capacitors (DTCs) in an inter-layer medium (ILM) on an interconnect layer of an integrated circuit (IC) die is disclosed. A method of fabricating an IC die comprising DTCs in the ILM is also disclosed. The DTCs are disposed on an IC, in an ILM, to minimize the lengths of the power and ground traces coupling the DTCs to circuits in a semiconductor layer. The DTCs and the semiconductor layer are on opposite sides of the metal layer(s) used to interconnect the circuits, so the locations of the DTCs in the ILM can be independent of circuit layout and interconnect routing. IC dies with DTCs disposed in the ILM can significantly reduce voltage droop and spikes in IC dies in an IC stack. In one example, DTCs are also located in trenches in the substrate of the IC die.

公开(公告)号：US09245971B2

公开(公告)日：2016-01-26

申请号：US14040366

申请日：2013-09-27

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  P R Chidambaram ,  John Jianhong Zhu ,  Jihong Choi ,  Da Yang ,  Ravi Mahendra Todi ,  Giridhar Nallapati ,  Chock Hing Gan ,  Ming Cai ,  Samit Sengupta

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/8238

CPC classification number: H01L29/66431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/778 ,  H01L29/7834

Abstract: In a particular embodiment, a semiconductor device includes a high mobility channel between a source region and a drain region. The high mobility channel extends substantially a length of a gate. The semiconductor device also includes a doped region extending from the source region or the drain region toward the high mobility channel. A portion of a substrate is positioned between the doped region and the high mobility channel.

Abstract translation: 在特定实施例中，半导体器件包括源极区和漏极区之间的高迁移率沟道。 高迁移率通道基本上延伸了一个门的长度。 半导体器件还包括从源极区域或漏极区域向高迁移率通道延伸的掺杂区域。 衬底的一部分位于掺杂区域和高迁移率通道之间。

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。