公开(公告)号：US20240078735A1

公开(公告)日：2024-03-07

申请号：US18067837

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Xuefeng Tang ,  Vishwanath Shashikant Nikam ,  Nigel Poole ,  Kalyan Kumar Bhiravabhatla ,  Fei Xu ,  Zilin Ying

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US20180189179A1

公开(公告)日：2018-07-05

申请号：US15423889

申请日：2017-02-03

Applicant: QUALCOMM Incorporated

Inventor： Yun Li ,  Jian Liang ,  Fei Xu ,  Zhen Chen ,  Chun Yu ,  Tao Wang

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0846

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/455

Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.

公开(公告)号：US10055342B2

公开(公告)日：2018-08-21

申请号：US14219696

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Alexei Vladimirovich Bourd ,  Swapnil Pradipkumar Sakharshete ,  Fei Xu

IPC: G06F12/02 ,  G06F9/54 ,  G06F9/52

CPC classification number: G06F12/023 ,  G06F9/526 ,  G06F9/54 ,  G06F9/546

Abstract: This disclosure describes techniques for supporting inter-task communication in a parallel computing system. The techniques for supporting inter-task communication may use hardware-based atomic operations to maintain the state of a pipe. A pipe may refer to a First-In, First-Out (FIFO)-organized buffer that allows various tasks to interact with the buffer as data producers or data consumers. Various pipe implementations may use multiple state parameters to define the state of a pipe. The hardware-based atomic operations described in this disclosure may modify multiple pipe state parameters in an atomic fashion. Modifying multiple pipe state parameters in an atomic fashion may avoid race conditions that would otherwise occur when multiple producers and/or multiple consumers attempt to modify the state of a pipe at the same time. In this way, pipe-based inter-task communication may be supported in a parallel computing system.

公开(公告)号：US20180174623A1

公开(公告)日：2018-06-21

申请号：US15381587

申请日：2016-12-16

Applicant: QUALCOMM Incorporated

Inventor： Fei Xu ,  Rakesh Vattikonda ,  Dina McKinney ,  Zhen Chen ,  Yun Li ,  Zhenbiao Ma ,  De Lu

IPC: G11C7/10 ,  G06F3/06

CPC classification number: G11C7/1012 ,  G11C7/222

Abstract: An apparatus and method are disclosed for transferring data from a first core to a second core of an integrated circuit (IC). The first core includes first and second memory blocks (e.g., first and second portions of a first-in-first-out (FIFO) memory coupled to first and second pre-multiplexers, respectively). The second core includes a multiplexer including first and second inputs coupled to the first and second memory blocks, respectively. Additionally, the second core includes a read controller configured to generate a first read control signal to cause the first and second memory blocks to transfer data to the first and second inputs of the multiplexer, respectively; and generate a second read control signal to cause the multiplexer to transfer data from the first and inputs to an output of the multiplexer.

公开(公告)号：US20150269065A1

公开(公告)日：2015-09-24

申请号：US14219696

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Alexei Vladimirovich Bourd ,  Swapnil Pradipkumar Sakharshete ,  Fei Xu

IPC: G06F12/02 ,  G06F9/54

CPC classification number: G06F12/023 ,  G06F9/526 ,  G06F9/54 ,  G06F9/546

Abstract: This disclosure describes techniques for supporting inter-task communication in a parallel computing system. The techniques for supporting inter-task communication may use hardware-based atomic operations to maintain the state of a pipe. A pipe may refer to a First-In, First-Out (FIFO)-organized buffer that allows various tasks to interact with the buffer as data producers or data consumers. Various pipe implementations may use multiple state parameters to define the state of a pipe. The hardware-based atomic operations described in this disclosure may modify multiple pipe state parameters in an atomic fashion. Modifying multiple pipe state parameters in an atomic fashion may avoid race conditions that would otherwise occur when multiple producers and/or multiple consumers attempt to modify the state of a pipe at the same time. In this way, pipe-based inter-task communication may be supported in a parallel computing system.

Abstract translation: 本公开描述了用于在并行计算系统中支持任务间通信的技术。 用于支持任务间通信的技术可以使用基于硬件的原子操作来维持管道的状态。 管道可以指先入先出（FIFO）组织的缓冲器，其允许各种任务与作为数据生成器或数据消费者的缓冲器进行交互。 各种管道实现可以使用多个状态参数来定义管道的状态。 在本公开中描述的基于硬件的原子操作可以以原子方式修改多个管状态参数。 以原子方式修改多个管道状态参数可以避免当多个生产者和/或多个消费者试图同时修改管道状态时会发生的竞争条件。 以这种方式，可以在并行计算系统中支持基于管道的任务间通信。

公开(公告)号：US09342461B2

公开(公告)日：2016-05-17

申请号：US13687761

申请日：2012-11-28

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Chun Yu ,  Fei Xu

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0886 ,  G06F12/0895 ,  G06F2212/604

Abstract: A cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller may include a dirty buffer index which stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated. A cache line may include a fully dirty flag indicating when each byte in that cache line is dirty, so that a dirty mask does not need to be allocated for that cache line.

Abstract translation: 高速缓冲存储器系统包括包括多个高速缓存存储器线的高速缓冲存储器和包括多个脏掩模的脏缓冲器。 高速缓存控制器被配置为当对相应高速缓存存储器线的写入不是对该高速缓存存储器线的完全写入时，将一个脏掩模分配给每个高速缓存存储器线。 每个脏屏蔽指示一个缓存存储器线中的数据单元的脏状态。 高速缓存控制器可以包括脏缓冲器索引，该脏缓冲器索引存储将脏掩码与分配有脏掩码的高速缓冲存储器线相关联的标识（ID）信息。 高速缓存行可以包括完全脏标志，指示该高速缓存行中的每个字节何时是脏的，从而不需要为该高速缓存行分配脏掩码。

公开(公告)号：US20140149685A1

公开(公告)日：2014-05-29

申请号：US13687761

申请日：2012-11-28

Applicant: QUALCOMM INCORPORATED

Inventor： Jian Liang ,  Chun Yu ,  Fei Xu

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0886 ,  G06F12/0895 ,  G06F2212/604

Abstract: Systems and methods related to a memory system including a cache memory are disclosed. The cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated.

Abstract translation: 公开了与包括高速缓冲存储器的存储器系统有关的系统和方法。 高速缓冲存储器系统包括包括多个高速缓存存储器线的高速缓存存储器和包括多个脏掩模的脏缓冲器。 高速缓存控制器被配置为当对相应高速缓存存储器线的写入不是对该高速缓存存储器线的完全写入时，将一个脏掩模分配给每个高速缓存存储器线。 每个脏屏蔽指示一个缓存存储器线中的数据单元的脏状态。 高速缓存控制器存储将脏屏蔽与分配有脏屏蔽的高速缓冲存储器线相关联的标识（ID）信息。