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    USB DEVICE WITH CLOCK DOMAIN CORRELATION
    4.
    发明申请
    USB DEVICE WITH CLOCK DOMAIN CORRELATION 审中-公开

    公开(公告)号：US20190025872A1

    公开(公告)日：2019-01-24

    申请号：US15652516

    申请日：2017-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Ren Li ,  Peter Shah ,  Matthew Sienko ,  Hui-ya Liao Nelson ,  Stefan Rohrer ,  Arash Mehrabi ,  Stefan Mueller ,  Ralf Herz ,  Magesh Hariharan ,  Maoxin Wei

    IPC: G06F1/12 ,  G06F13/42

    Abstract: Methods and USB devices correlating clock domains are presented. A USB device includes at least one signal line adapted to carry signals in a first clock domain. The signals are received from a USB host. A clock operates a second clock domain. A periodic packet detection circuit detects a missing periodic packet from the signals received in the first clock domain. A device controller correlates a USB operation in the second clock domain with the first clock domain based on the periodic packet detection circuit detecting the missing periodic packet. A USB device includes at least one signal line carrying UTMI or ULPI signaling. A USB controller decodes packet identification from the UTMI or ULPI signaling. A periodic packet detection circuit, separate from the USB controller, decodes packet identification from the UTMI or ULPI signaling.

    RC OSCILLATOR BASED ON DELAY-FREE COMPARATOR
    5.
    发明申请
    RC OSCILLATOR BASED ON DELAY-FREE COMPARATOR 有权
    RC振荡器基于无延迟比较器

    公开(公告)号：US20150349710A1

    公开(公告)日：2015-12-03

    申请号：US14290665

    申请日：2014-05-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Le Wang ,  Arash Mehrabi

    IPC: H03B5/04 ,  H03B5/20

    CPC classification number: H03B5/04 ,  H03B5/20 ,  H03K3/0231 ,  H03K3/30 ,  H03K4/50 ,  H04B5/04

    Abstract: Cancelling a delay in a comparator of an RC oscillator configured to generate a clock pulse, including: selectively coupling a plurality of current sources to a first capacitor, a second capacitor, and a resistor, wherein the plurality of current source charge and discharge the first capacitor and the second capacitor, and charge the resistor; charging the first capacitor at a higher rate during a first phase of the clock pulse than a second phase of the clock pulse, and charging the second capacitor at a higher rate during a third phase of the clock pulse than a fourth phase of the clock pulse; and generating the clock pulse by enabling the comparator to compare a voltage on the first or second capacitor with a voltage on the resistor.

    Abstract translation: 取消被配置为产生时钟脉冲的RC振荡器的比较器中的延迟，包括：选择性地将多个电流源耦合到第一电容器，第二电容器和电阻器，其中所述多个电流源对第一 电容器和第二电容器，并对电阻充电; 在时钟脉冲的第一相位期间以比时钟脉冲的第二相位更高的速率对第一电容器充电，并且在时钟脉冲的第三相位期间以比时钟脉冲的第四相位更高的速率对第二电容器充电 ; 并通过使比较器将第一或第二电容器上的电压与电阻器上的电压进行比较来产生时钟脉冲。

    DEVICE PLUG DETECTION APPARATUS AND METHOD
    6.
    发明申请
    DEVICE PLUG DETECTION APPARATUS AND METHOD 有权
    设备插件检测装置和方法

    公开(公告)号：US20130320993A1

    公开(公告)日：2013-12-05

    申请号：US13675995

    申请日：2012-11-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Arash Mehrabi

    IPC: G01R31/04 ,  H01R13/70

    CPC classification number: G01R31/04 ,  H01R13/70 ,  H01R13/7031 ,  H01R24/58 ,  H01R2107/00 ,  H01R2201/16 ,  H04M1/6058 ,  H04M1/72527 ,  H04R5/04 ,  H04R2420/05

    Abstract: A particular apparatus includes a receptacle having a first pin configured to contact a tip region of the device plug at a first location when the device plug is inserted into the receptacle. The first location may be located between a midpoint of the tip region and a tip of the device plug. The receptacle further includes a second pin configured to contact a second region of the device plug at a second location. The receptacle further includes a third pin configured to contact a third region of the device plug at a third location. The receptacle further includes a fourth pin configured to contact a fourth region of the device.

    Abstract translation: 特定装置包括具有第一销的插座，该第一插脚构造成当装置插头插入插座时在第一位置处接触装置插头的尖端区域。 第一位置可以位于尖端区域的中点和设备插头的尖端之间。 插座还包括第二引脚，其构造成在第二位置处接触设备插头的第二区域。 插座还包括构造成在第三位置处接触设备插头的第三区域的第三引脚。 插座还包括被配置为接触设备的第四区域的第四引脚。

    INTEGRATED TRANSIENT VOLTAGE SUPPRESSOR CIRCUIT
    8.
    发明申请
    INTEGRATED TRANSIENT VOLTAGE SUPPRESSOR CIRCUIT 审中-公开

    公开(公告)号：US20180374705A1

    公开(公告)日：2018-12-27

    申请号：US15632040

    申请日：2017-06-23

    Applicant: QUALCOMM Incorporated

    Inventor： Vijayakumar Dhanasekaran ,  Ramkumar Sivakumar ,  Arash Mehrabi

    IPC: H01L21/265 ,  H01L27/08 ,  H01L29/93 ,  H01L29/861 ,  H01L27/02 ,  H01L29/87 ,  H01L29/06

    Abstract: A transient signal protection circuit includes an input node coupled to a signal line configured to carry an output signal from a first circuit to a second circuit, wherein the signal line is subject to experiencing an unwanted reverse signal from the second circuit to the first circuit. The transient signal protection circuit also includes a comparator module configured to output a clamping signal when it is determined that the unwanted reverse signal includes a value that falls outside an acceptable range of the first circuit; and a power switch coupled to the comparator module and configured to couple the input node to a sink node when the comparator module outputs the clamping signal.

    Multi-stage switched-capacitor DC blocking circuit for audio frontend
    10.
    发明授权
    Multi-stage switched-capacitor DC blocking circuit for audio frontend 有权
    用于音频前端的多级开关电容器直流阻塞电路

    公开(公告)号：US09391569B2

    公开(公告)日：2016-07-12

    申请号：US14230909

    申请日：2014-03-31

    Applicant: QUALCOMM Incorporated

    Inventor： Meysam Azin ,  Arash Mehrabi ,  Wenchang Huang

    IPC: H03F1/02 ,  H03F3/185 ,  H03F3/45 ,  H03F3/00 ,  H03F3/181 ,  H03F3/187 ,  H03H19/00 ,  H04R3/00

    CPC classification number: H03F3/185 ,  H03F3/005 ,  H03F3/181 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/03 ,  H03F2203/45016 ,  H03F2203/45514 ,  H03H19/004 ,  H04R3/00

    Abstract: An integrated DC blocking amplifier circuit, including: an operational amplifier configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit and a second-stage circuit, wherein the first two-stage switched capacitor circuit is connected to a positive side feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative side feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.

    Abstract translation: 一种集成的DC阻塞放大器电路，包括：配置在差分放大器中的运算放大器; 以及至少第一和第二两级开关电容器电路，每个两级开关电容器电路包括第一级电路和第二级电路，其中所述第一两级开关电容器电路连接到正侧反馈 运算放大器和第二两级开关电容电路的路径连接到运算放大器的负侧反馈路径，其中第一级电路以相对低的开关频率切换，而第二级电路被切换 在相对高的开关频率。

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