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    RF power detector
    1.
    发明授权
    RF power detector 有权

    公开(公告)号：US11451310B1

    公开(公告)日：2022-09-20

    申请号：US17207121

    申请日：2021-03-19

    Applicant: QUALCOMM Incorporated

    Inventor： Peter Shah

    IPC: H04B1/04 ,  H04B17/10 ,  G01R21/00 ,  H04W24/02 ,  H03G3/30

    Abstract: An RF power detector controls an amplitude of a replica input signal so that a power of the replica input signal substantially equals a power of an input signal to the RF power detector. A signal generator generates the replica input signal responsive to a digital control word. A feedback circuit adjusts the digital control word responsive to a comparison of output signals from an analog power sensor.

    Jammer detection system
    3.
    发明授权
    Jammer detection system 有权

    公开(公告)号：US12107673B2

    公开(公告)日：2024-10-01

    申请号：US17468281

    申请日：2021-09-07

    Applicant: QUALCOMM Incorporated

    Inventor： Peter Shah ,  Ajay Devadatta Kanetkar ,  Siavash Ekbatani ,  Yuanning Yu ,  Shrenik Patel ,  Dongjiang Qiao ,  Rajagopalan Rangarajan

    IPC: H04K3/00 ,  H04B17/318

    CPC classification number: H04K3/22 ,  H04B17/318 ,  H04K3/45

    Abstract: Certain aspects of the present disclosure generally relate to jamming detection for radio frequency (RF) front-end circuitry. For example, certain aspects provide an apparatus having a first counter configured to count a number of times that a power of a reception signal exceeds a first threshold. The apparatus also includes a second counter configured to count a number of measurements of the power of the reception signal. The apparatus further includes control logic having a first input coupled to an output of the first counter and having a second input coupled to an output of the second counter. The control logic is configured to determine an amount of jamming over a measurement window based on the number of times that the power of the reception signal exceeds the first threshold and on the number of measurements.

    USB DEVICE WITH CLOCK DOMAIN CORRELATION
    5.
    发明申请
    USB DEVICE WITH CLOCK DOMAIN CORRELATION 审中-公开

    公开(公告)号：US20190025872A1

    公开(公告)日：2019-01-24

    申请号：US15652516

    申请日：2017-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Ren Li ,  Peter Shah ,  Matthew Sienko ,  Hui-ya Liao Nelson ,  Stefan Rohrer ,  Arash Mehrabi ,  Stefan Mueller ,  Ralf Herz ,  Magesh Hariharan ,  Maoxin Wei

    IPC: G06F1/12 ,  G06F13/42

    Abstract: Methods and USB devices correlating clock domains are presented. A USB device includes at least one signal line adapted to carry signals in a first clock domain. The signals are received from a USB host. A clock operates a second clock domain. A periodic packet detection circuit detects a missing periodic packet from the signals received in the first clock domain. A device controller correlates a USB operation in the second clock domain with the first clock domain based on the periodic packet detection circuit detecting the missing periodic packet. A USB device includes at least one signal line carrying UTMI or ULPI signaling. A USB controller decodes packet identification from the UTMI or ULPI signaling. A periodic packet detection circuit, separate from the USB controller, decodes packet identification from the UTMI or ULPI signaling.

    Combined I/Q Digital-to-Analog Converter
    7.
    发明申请
    Combined I/Q Digital-to-Analog Converter 有权

    公开(公告)号：US20230085720A1

    公开(公告)日：2023-03-23

    申请号：US17448683

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Peter Shah ,  Matthew Sienko

    IPC: H03M1/06

    Abstract: A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

    Combined I/Q digital-to-analog converter
    9.
    发明授权
    Combined I/Q digital-to-analog converter 有权

    公开(公告)号：US11677408B2

    公开(公告)日：2023-06-13

    申请号：US17448683

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Peter Shah ,  Matthew Sienko

    IPC: H03M1/66 ,  H03M1/06

    CPC classification number: H03M1/0617 ,  H03M1/12 ,  H03M1/004

    Abstract: A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

    RF SQUARE-LAW CIRCUIT
    10.
    发明申请
    RF SQUARE-LAW CIRCUIT 审中-公开

    公开(公告)号：US20200073428A1

    公开(公告)日：2020-03-05

    申请号：US16356435

    申请日：2019-03-18

    Applicant: QUALCOMM Incorporated

    Inventor： Mohamed Abouzied ,  Rajagopalan Rangarajan ,  Peter Shah

    IPC: G05F3/26 ,  G05F3/24 ,  H04B17/13

    Abstract: A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

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