公开(公告)号：US20230085720A1

公开(公告)日：2023-03-23

申请号：US17448683

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Peter Shah ,  Matthew Sienko

IPC: H03M1/06

Abstract: A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

公开(公告)号：US10164650B2

公开(公告)日：2018-12-25

申请号：US15435155

申请日：2017-02-16

Applicant: QUALCOMM Incorporated

Inventor： Jingxue Lu ,  Matthew Sienko

IPC: H03M1/06 ,  H03M3/00

Abstract: A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

公开(公告)号：US11677408B2

公开(公告)日：2023-06-13

申请号：US17448683

申请日：2021-09-23

Applicant: QUALCOMM Incorporated

Inventor： Peter Shah ,  Matthew Sienko

IPC: H03M1/66 ,  H03M1/06

CPC classification number: H03M1/0617 ,  H03M1/12 ,  H03M1/004

Abstract: A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

公开(公告)号：US20180234101A1

公开(公告)日：2018-08-16

申请号：US15435155

申请日：2017-02-16

Applicant: QUALCOMM Incorporated

Inventor： Jingxue Lu ,  Matthew Sienko

IPC: H03M1/06 ,  H03M3/00

CPC classification number: H03M1/0617 ,  H03M3/42 ,  H03M3/432 ,  H03M3/47 ,  H03M3/50

Abstract: A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.

公开(公告)号：US11502717B2

公开(公告)日：2022-11-15

申请号：US17156352

申请日：2021-01-22

Applicant: QUALCOMM Incorporated

Inventor： Matthew Sienko ,  Peter Shah ,  Francesco Gatta

IPC: H04B1/40 ,  H04L27/227

Abstract: A switching mixer array is disclosed for the mixing of a digital LO signal with an analog input signal. Each switching mixer in the array is configured to assume either a first switching state or second switching state responsive to a respective bit of the digital LO signal.

公开(公告)号：US20190025872A1

公开(公告)日：2019-01-24

申请号：US15652516

申请日：2017-07-18

Applicant: QUALCOMM Incorporated

Inventor： Ren Li ,  Peter Shah ,  Matthew Sienko ,  Hui-ya Liao Nelson ,  Stefan Rohrer ,  Arash Mehrabi ,  Stefan Mueller ,  Ralf Herz ,  Magesh Hariharan ,  Maoxin Wei

IPC: G06F1/12 ,  G06F13/42

Abstract: Methods and USB devices correlating clock domains are presented. A USB device includes at least one signal line adapted to carry signals in a first clock domain. The signals are received from a USB host. A clock operates a second clock domain. A periodic packet detection circuit detects a missing periodic packet from the signals received in the first clock domain. A device controller correlates a USB operation in the second clock domain with the first clock domain based on the periodic packet detection circuit detecting the missing periodic packet. A USB device includes at least one signal line carrying UTMI or ULPI signaling. A USB controller decodes packet identification from the UTMI or ULPI signaling. A periodic packet detection circuit, separate from the USB controller, decodes packet identification from the UTMI or ULPI signaling.