公开(公告)号：US11894070B2

公开(公告)日：2024-02-06

申请号：US18156654

申请日：2023-01-19

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Tsukasa Kobayashi ,  Koji Kato ,  Yuki Shimizu ,  Hiroshi Maejima

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11133066B2

公开(公告)日：2021-09-28

申请号：US16934978

申请日：2020-07-21

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11594285B2

公开(公告)日：2023-02-28

申请号：US17481892

申请日：2021-09-22

Applicant: Kioxia Corporation

Inventor： Takeshi Hioka ,  Tsukasa Kobayashi ,  Koji Kato ,  Yuki Shimizu ,  Hiroshi Maejima

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11568 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US11423980B2

公开(公告)日：2022-08-23

申请号：US17184246

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Kosuke Yanagidaira

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor storage device includes a first plane storing user data and system information, a second plane storing the user data and the system information, a first latch circuit storing even-numbered bit data of the system information read from the first plane, a second latch circuit storing odd-numbered bit data of the system information read from the second plane, and a sequencer. The sequencer executes in parallel a first process of reading out the even-numbered bit data of the system information from the first plane and storing the read data in the first latch circuit and a second process of reading out the odd-numbered bit data of the system information from the second plane and storing the read data in the second latch circuit.