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    USING A SAME MASK FOR DIRECT PRINT AND SELF-ALIGNED DOUBLE PATTERNING OF NANOSHEETS
    2.
    发明申请
    USING A SAME MASK FOR DIRECT PRINT AND SELF-ALIGNED DOUBLE PATTERNING OF NANOSHEETS 有权

    公开(公告)号：US20220102153A1

    公开(公告)日：2022-03-31

    申请号：US17546443

    申请日：2021-12-09

    申请人： International Business Machines Corporation

    发明人： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

    IPC分类号： H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

    摘要： A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.

    STRUCTURE CONTAINING A VIA-TO-BURIED POWER RAIL CONTACT STRUCTURE OR A VIA-TO-BACKSIDE POWER RAIL CONTACT STRUCTURE
    3.
    发明申请
    STRUCTURE CONTAINING A VIA-TO-BURIED POWER RAIL CONTACT STRUCTURE OR A VIA-TO-BACKSIDE POWER RAIL CONTACT STRUCTURE 有权

    公开(公告)号：US20230139929A1

    公开(公告)日：2023-05-04

    申请号：US17512744

    申请日：2021-10-28

    申请人： International Business Machines Corporation

    发明人： Ruilong Xie ,  Stuart Sieg ,  Kevin Shawn Petrarca ,  Eric Miller

    IPC分类号： H01L23/48 ,  H01L29/66 ,  H01L29/06 ,  H01L27/12

    摘要： A semiconductor structure is provided in which a via to buried power rail (VBPR) contact structure is present that has a via portion contacting a buried power rail and a non-via portion contacting a source/drain region of a first functional gate structure present in a first device region. A dielectric spacer structure including a base dielectric spacer and a replacement dielectric spacer is located between the VPBR contact structure and the first functional gate structure. The replacement dielectric spacer is composed of a gate cut trench dielectric material that is also present in a gate cut trench that is located between the first functional gate structure present in the first device region, and a second functional gate structure that is present in a second device region. The replacement dielectric spacer replaces a damaged region of a dielectric spacer that is originally present during VBPR formation.

    STRUCTURE AND METHOD TO PATTERN PITCH LINES
    4.
    发明申请
    STRUCTURE AND METHOD TO PATTERN PITCH LINES 有权

    公开(公告)号：US20230138978A1

    公开(公告)日：2023-05-04

    申请号：US17453010

    申请日：2021-11-01

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： CHANRO PARK ,  Chi-Chun LIU ,  Stuart Sieg ,  Yann Mignot ,  Koichi Motoyama ,  Hsueh-Chung Chen

    IPC分类号： H01L21/033 ,  H01L21/3213

    摘要： A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

    USING A SAME MASK FOR DIRECT PRINT AND SELF-ALIGNED DOUBLE PATTERNING OF NANOSHEETS
    5.
    发明申请
    USING A SAME MASK FOR DIRECT PRINT AND SELF-ALIGNED DOUBLE PATTERNING OF NANOSHEETS 有权

    公开(公告)号：US20210020446A1

    公开(公告)日：2021-01-21

    申请号：US16514235

    申请日：2019-07-17

    申请人： International Business Machines Corporation

    发明人： Stuart Sieg ,  Daniel James Dechene ,  Eric Miller

    IPC分类号： H01L21/308 ,  H01L27/092 ,  H01L21/033 ,  H01L21/8234

    摘要： A method of forming a semiconductor structure includes forming a nanosheet stack including alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors. The method also includes forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack. The method further includes patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning. The second width is less than the first width.