公开(公告)号：US12142545B2

公开(公告)日：2024-11-12

申请号：US18238726

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L25/18

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US20240006323A1

公开(公告)日：2024-01-04

申请号：US17853018

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Naren Sreenivas Viswanathan ,  Sujit Sharan ,  Jiwei Sun

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L23/5383 ,  H01L25/0655

Abstract: An electronic device may include an interconnect bridge. The interconnect bridge may include a first electrical routing trace having a first routing length and a corresponding first transit time for a first electrical signal to transmit across the first routing length. The first electrical routing trace may transmit the first electrical signal along a major plane of the interconnect bridge between a first interconnect and a second interconnect. The interconnect bridge may include a routing trace deviation in communication with the first electrical routing trace. The routing trace deviation is outside a direct route between the first interconnect and the second interconnect. The routing trace deviation may alter one or more of capacitance or resistance of the first electrical routing trace and correspondingly alter the first routing time.

公开(公告)号：US11798865B2

公开(公告)日：2023-10-24

申请号：US16291314

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11742261B2

公开(公告)日：2023-08-29

申请号：US18089535

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Ravindranath Mahajan ,  Debendra Mallik ,  Sujit Sharan ,  Digvijay Raorane

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/565 ,  H01L21/76898 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/17 ,  H01L24/29 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/73253

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US11355427B2

公开(公告)日：2022-06-07

申请号：US16095916

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Howe Yin Loo ,  Sujit Sharan ,  Tin Poay Chuah ,  Ananth Prabhakumar

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18 ,  H01L25/065

Abstract: Techniques and mechanisms to facilitate connectivity between circuit components via a substrate. In an embodiment, a microelectronic device includes a substrate, wherein a recess region extends from the first side of the substrate and only partially toward a second side of the substrate. First input/output (IO) contacts of a first hardware interface are disposed in the recess region. The first IO contacts are variously coupled to each to a respective metallization layer of the substrate, wherein the recess region extends though one or more other metallization layers of the substrate. In another embodiment, the microelectronic device further comprises second IO contacts of a second hardware interface, the second IO contacts to couple the microelectronic device to a printed circuit board.

公开(公告)号：US10797014B2

公开(公告)日：2020-10-06

申请号：US16320680

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Dae-Woo Kim ,  Ajay Jain ,  Neha M. Patel ,  Rodrick J. Hendricks ,  Sujit Sharan

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises a first integrated circuit die and a second integrated circuit die. The integrated circuit package further includes a substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the substrate. The substrate includes an interconnect bridge embedded within the substrate, wherein the interconnect bridge includes at least one metal trace component, wherein the metal trace component includes rounded corners on a bottom portion of the metal trace component.

公开(公告)号：US10651117B2

公开(公告)日：2020-05-12

申请号：US16015739

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Andrew Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L23/498 ,  H01L23/42 ,  H01L21/48 ,  H01L25/16 ,  H01L49/02

Abstract: A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

公开(公告)号：US20200006302A1

公开(公告)日：2020-01-02

申请号：US16022677

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew P. Collins ,  Jianyong Xie ,  Sujit Sharan

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/64

Abstract: A package is disclosed. The package includes a base die. The base die includes voltage regulating circuitry and input and output (I/O) circuitry. The I/O circuitry surrounds the voltage regulating circuitry. The package also includes a top set of dies. The top set of dies includes a plurality of dies that include logic circuitry and a plurality of dies that include passive components. The plurality of dies that include passive components surround the plurality of dies that include logic circuitry. The plurality of dies that includes passive components is coupled to the logic circuitry and to the voltage regulating circuitry.

公开(公告)号：US20190318993A1

公开(公告)日：2019-10-17

申请号：US16469084

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Zhiguo Qian ,  Henning Braunisch ,  Kemal Aygun ,  Sujit Sharan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

公开(公告)号：US09711443B2

公开(公告)日：2017-07-18

申请号：US14941571

申请日：2015-11-14

Applicant: Intel Corporation

Inventor： Ankur Agrawal ,  Srinivas S. Moola ,  Sujit Sharan ,  Vijay Govindarajan

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/02

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L23/02 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/564 ,  H01L24/16 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate.