Invention Grant
- Patent Title: Nested architectures for enhanced heterogeneous integration
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Application No.: US18238726Application Date: 2023-08-28
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Publication No.: US12142545B2Publication Date: 2024-11-12
- Inventor: Ravindranath Mahajan , Debendra Mallik , Sujit Sharan , Digvijay Raorane
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/56 ; H01L21/768 ; H01L23/00 ; H01L23/31 ; H01L23/34 ; H01L23/538 ; H01L25/18

Abstract:
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
Public/Granted literature
- US20230411245A1 NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION Public/Granted day:2023-12-21
Information query
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