公开(公告)号：US20230071699A1

公开(公告)日：2023-03-09

申请号：US17470993

申请日：2021-09-09

申请人： Intel Corporation

发明人： Andrew Smith ,  Brian Greene ,  Seonghyun Paik ,  Omair Saadat ,  Chung-Hsun Lin ,  Tahir Ghani

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

摘要： A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.

公开(公告)号：US12113068B2

公开(公告)日：2024-10-08

申请号：US17031832

申请日：2020-09-24

申请人： Intel Corporation

发明人： Dan S. Lavric ,  Dax M. Crum ,  Omair Saadat ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L27/092 ,  B82Y10/00 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

申请人： Intel Corporation

发明人： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

申请人： Intel Corporation

发明人： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

摘要： Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.