公开(公告)号：US08942027B1

公开(公告)日：2015-01-27

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C11/00 ,  G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US20150016176A1

公开(公告)日：2015-01-15

申请号：US13939062

申请日：2013-07-10

Applicant: Industrial Technology Research Institute

Inventor： Ching-Hao Chuang ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Zhe-Hui Lin

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/009 ,  G11C11/16 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0069 ,  G11C14/0081

Abstract: A memory storage circuit includes a volatile memory portion, a control portion, and a non-volatile memory portion. The volatile memory portion includes a first node and a second node to store a pair of complementary logic data. The control portion includes a first transistor and a second transistor. Gate electrodes of the first and second transistors are coupled to receive a store signal, and first electrodes of the first and second transistors are coupled to receive a control signal. The non-volatile memory portion includes a first resistive memory element and a second resistive memory element to store the pair of complementary logic data. The first resistive memory element is coupled between a second electrode of the first transistor and the first node, and the second resistive memory element is coupled between a second electrode of the second transistor and the second node.

Abstract translation: 存储器存储电路包括易失性存储器部分，控制部分和非易失性存储器部分。 易失性存储器部分包括存储一对互补逻辑数据的第一节点和第二节点。 控制部分包括第一晶体管和第二晶体管。 第一晶体管和第二晶体管的栅电极被耦合以接收存储信号，并且第一和第二晶体管的第一电极被耦合以接收控制信号。 非易失性存储器部分包括第一电阻存储器元件和第二电阻存储元件，用于存储该对互补逻辑数据。 第一电阻性存储元件耦合在第一晶体管的第二电极和第一节点之间，而第二电阻存储元件耦合在第二晶体管的第二电极和第二节点之间。

公开(公告)号：US09443588B2

公开(公告)日：2016-09-13

申请号：US14749651

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Pei-Ling Tseng ,  Chia-Chen Kuo ,  Shyh-Shyuan Sheu ,  Meng-Fan Chang

IPC: G11C11/00 ,  G11C11/36 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

Abstract translation: 提供了一种电阻式存储器系统，其驱动电路及其电阻设定方法。 电阻式存储器系统包括存储器阵列，行选择电路，第一控制电路和第二控制电路。 存储器阵列具有多个电阻存储单元。 行选择电路用于激活电阻式存储单元。 第一控制电路和第二控制电路耦合到电阻存储器单元。 当每个电阻性存储器单元被设置时，第一控制电路和第二控制电路分别向每个电阻存储器单元提供一个设定电压和一个接地电压以形成一个设定电流，并且将该设定电流钳位在至少一个 的第一控制电路和第二控制电路。

公开(公告)号：US20160118120A1

公开(公告)日：2016-04-28

申请号：US14749651

申请日：2015-06-25

Applicant: Industrial Technology Research Institute

Inventor： Pei-Ling Tseng ,  Chia-Chen Kuo ,  Shyh-Shyuan Sheu ,  Meng-Fan Chang

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/79

Abstract: A resistive memory system, a driver circuit thereof and a method for setting resistances thereof are provided. The resistive memory system includes a memory array, a row selection circuit, a first control circuit and a second control circuit. The memory array has a plurality of resistive memory cells. The row selection circuit is used for activating the resistive memory cells. The first control circuit and the second control circuit are coupled to the resistive memory cells. When each of resistive memory cells is set, the first control circuit and the second control circuit respectively provide a set voltage and a ground voltage to the each of resistive memory cells to form a set current, and the set current is clamped by at least one of the first control circuit and the second control circuit.

Abstract translation: 提供了一种电阻式存储器系统，其驱动电路及其电阻设定方法。 电阻式存储器系统包括存储器阵列，行选择电路，第一控制电路和第二控制电路。 存储器阵列具有多个电阻存储单元。 行选择电路用于激活电阻式存储单元。 第一控制电路和第二控制电路耦合到电阻存储器单元。 当每个电阻性存储器单元被设置时，第一控制电路和第二控制电路分别向每个电阻存储器单元提供一个设定电压和一个接地电压以形成一个设定电流，并且将该设定电流钳位在至少一个 的第一控制电路和第二控制电路。