公开(公告)号：US10162914B1

公开(公告)日：2018-12-25

申请号：US15673467

申请日：2017-08-10

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Suparn Vats

IPC: G01R31/3177 ,  G06F17/50 ,  G06F17/30 ,  H03K19/003 ,  G01R31/3183 ,  G01R31/3185

Abstract: A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.

公开(公告)号：US20200373915A1

公开(公告)日：2020-11-26

申请号：US16989621

申请日：2020-08-10

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/28 ,  G06F1/08

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US09672305B1

公开(公告)日：2017-06-06

申请号：US14607278

申请日：2015-01-28

Applicant: Apple Inc.

Inventor： Suparn Vats ,  Daniel J. Flees ,  Rohit Kumar

IPC: G06F17/50 ,  H03L7/00 ,  G06F1/32

CPC classification number: G06F17/505 ,  G06F1/3237 ,  G06F17/50 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045 ,  G06F17/5059 ,  G06F2217/62 ,  G06F2217/78 ,  G06F2217/84 ,  H03L7/00

Abstract: A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.

公开(公告)号：US11870442B2

公开(公告)日：2024-01-09

申请号：US17812089

申请日：2022-07-12

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/28 ,  G06F1/08

CPC classification number: H03K3/0372 ,  G06F1/08 ,  G06F1/28

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US20220345117A1

公开(公告)日：2022-10-27

申请号：US17812089

申请日：2022-07-12

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/28 ,  G06F1/08

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US11418173B2

公开(公告)日：2022-08-16

申请号：US16989621

申请日：2020-08-10

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: G06F1/08 ,  H03K3/037 ,  G06F1/28

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US10742201B2

公开(公告)日：2020-08-11

申请号：US16243954

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: G11C7/22 ,  H03K3/037 ,  G06F1/28 ,  G06F1/08

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US20200106425A1

公开(公告)日：2020-04-02

申请号：US16243954

申请日：2019-01-09

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Raghava Rao V. Denduluri ,  Ajay Bhatia ,  Suparn Vats ,  Suresh Balasubramanian ,  Gopinath Venkatesh ,  Teng Wang

IPC: H03K3/037 ,  G06F1/08 ,  G06F1/28

Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.

公开(公告)号：US10396778B1

公开(公告)日：2019-08-27

申请号：US15609687

申请日：2017-05-31

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Suparn Vats ,  Sangeetha Mani

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/20 ,  G11C5/14 ,  H03K19/23 ,  G11C11/413 ,  G06F17/50 ,  H03K17/687

Abstract: A device is disclosed that includes a circuit block coupled to a local power node, and a power gating circuit coupled between the local power node and a global power supply. In one embodiment, the power gating circuit includes a first plurality of first switching devices with a first threshold voltage, and a second plurality of second switching devices with a second threshold voltage that is different from the first voltage threshold. The power gating circuit may isolate the local power node from the global power supply based on an isolation signal.