公开(公告)号：US20250096096A1

公开(公告)日：2025-03-20

申请号：US18469243

申请日：2023-09-18

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Seongmin Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: Electronic packages and methods of formation are described. In an embodiment, an electronic package includes one or more electronic components encapsulated in a step molded molding compound layer, and wiring layer spanning a lower step surface, sidewall, and top surface of the step molded molding compound layer. The wiring layer may further extend into a via opening extending through the lower step surface of the molding compound layer.

公开(公告)号：US11532563B2

公开(公告)日：2022-12-20

申请号：US17026708

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai ,  Rajasekaran Swaminathan

IPC: H01L23/538 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56 ,  H01L25/16

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

公开(公告)号：US11515261B2

公开(公告)日：2022-11-29

申请号：US17027097

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai

IPC: H01L23/538 ,  H01L25/16 ,  H05K1/18 ,  H01L21/56 ,  H01L23/485

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

公开(公告)号：US20200107436A1

公开(公告)日：2020-04-02

申请号：US16375503

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Yinjuan He ,  Karthik Shanmugam ,  Peter R. Harper ,  Tongbi Tom Jiang

IPC: H05K1/02 ,  H01L33/24 ,  H01L25/16 ,  H01L23/31 ,  H01L33/08 ,  H01L33/62

Abstract: A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.

公开(公告)号：US12074077B2

公开(公告)日：2024-08-27

申请号：US16952567

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Flynn P. Carson ,  Jun Zhai ,  Raymundo M. Camenforte ,  Menglu Li

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/105 ,  H05K1/0278 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/24137 ,  H01L2225/06548 ,  H01L2924/18162

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：US20220093523A1

公开(公告)日：2022-03-24

申请号：US17027097

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L23/485 ,  H05K1/18

Abstract: One or more stud bumps may form a conductive column to a component having back side metallization. In an embodiment, the column of stud bumps may be about 130 um vertically (Z-direction). Providing a microelectronics package with a column of stud bumps electrically connected to a component having back side metallization may provide a cost effective electrical interconnect and may enable the incorporation of components of different thicknesses, including that the component thicknesses are independent of each other, in a single fanout package, while providing a thin package profile and back side surface finish integration.

公开(公告)号：US20220093522A1

公开(公告)日：2022-03-24

申请号：US17026708

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai ,  Rajasekaran Swaminathan

IPC: H01L23/538 ,  H01L23/31 ,  H05K1/18 ,  H01L25/16 ,  H01L21/56

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

公开(公告)号：US10811400B2

公开(公告)日：2020-10-20

申请号：US16375503

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Yinjuan He ,  Karthik Shanmugam ,  Peter R. Harper ,  Tongbi Tom Jiang

IPC: H01L31/12 ,  H01L25/16 ,  H01L33/24 ,  H01L33/62 ,  H01L23/31 ,  H01L33/08 ,  H01L31/18 ,  H01L33/00 ,  H01L27/15

Abstract: A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.

公开(公告)号：US12165956B2

公开(公告)日：2024-12-10

申请号：US17643247

申请日：2021-12-08

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Menglu Li ,  Raymundo M. Camenforte ,  Scott D. Morrison

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L25/16 ,  H01L49/02

Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

公开(公告)号：US20230178458A1

公开(公告)日：2023-06-08

申请号：US17643247

申请日：2021-12-08

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Menglu Li ,  Raymundo M. Camenforte ,  Scott D. Morrison

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/4952 ,  H01L23/31 ,  H01L23/5381 ,  H01L23/53228 ,  H01L28/00

Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.