公开(公告)号：US11009938B1

公开(公告)日：2021-05-18

申请号：US16139631

申请日：2018-09-24

Applicant: Apple Inc.

Inventor： Patrick Y. Law ,  Robert A. Drebin ,  Keith Cox ,  James S. Ismail

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3218 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

公开(公告)号：US20200379534A1

公开(公告)日：2020-12-03

申请号：US16889232

申请日：2020-06-01

Applicant: Apple Inc.

Inventor： Achmed R. Zahir ,  Diwakar N. Tundlam ,  James S. Ismail ,  Keith Cox ,  Reza Arastoo ,  Douglas A. MacKay ,  John M. Ananny ,  Michael Eng

IPC: G06F1/28 ,  G06F1/3212 ,  H02J7/00 ,  G01R31/387 ,  G01R31/367

Abstract: Systems and methods are disclosed for allocating and distributing power management budgets for subsystems (e.g., power usage clients) of a computer system. A power budget allocation subsystem may include a plurality of feedback branches having different associated time constants. Power usage clients with slower power response times may be provided power budgets based on a feedback branch having an associated longer time constant, while power usage clients with faster power response times may be provided with power budgets based on a feedback branch having an associated shorter time constant. The power budgets may be determined in the feedback branches based on power budgeting policies weighting the power budget of each subsystem relative to total power mitigation.

公开(公告)号：US10671131B2

公开(公告)日：2020-06-02

申请号：US14871526

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Nagarajan Kalyanasundaram ,  Jay S. Nigen ,  James S. Ismail ,  Richard H. Tan

IPC: G06F1/20 ,  G06F1/329 ,  G06F1/3296

Abstract: Systems and methods are disclosed for determining a current machine state of a processing device, predicting a future processing task to be performed by the processing device at a future time, and predicting a list of intervening processing tasks to be performed by a first time (e.g. a current time) and the start of the future processing task. The future processing task has an associated initial state. A feed-forward thermal prediction model determines a predicted future machine state at the time for starting the future processing task. Heat mitigation processes can be applied in advance of the starting of the future processing task, to meet the future initial machine state for starting the future processing task.

公开(公告)号：US20240427391A1

公开(公告)日：2024-12-26

申请号：US18438782

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Carmel Yamberger ,  Daniele Perretta ,  Jan Krellner ,  Ron Neuman ,  James S. Ismail ,  Keith Cox

IPC: G06F1/20 ,  G06F1/28 ,  G06F11/30

Abstract: Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.

公开(公告)号：US10895903B2

公开(公告)日：2021-01-19

申请号：US16266248

申请日：2019-02-04

Applicant: Apple Inc.

Inventor： James S. Ismail ,  John M. Ananny ,  John G. Dorsey ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Keith Cox ,  Inder M. Sodhi ,  Achmed R. Zahir

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G01R21/133

Abstract: In an embodiment, an electronic device includes a package power zone controller. The device monitors the overall power consumption of multiple components of a “package.” The package power zone controller may detect workloads in which the package components (e.g. different types of processors, peripheral hardware, etc.) are each consuming relatively low levels of power, but the overall power consumption is greater than a desired target. The package power zone controller may implement various mechanisms to reduce power consumption in such cases.

公开(公告)号：US20160357232A1

公开(公告)日：2016-12-08

申请号：US14871526

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Nagarajan Kalyanasundaram ,  Jay S. Nigen ,  James S. Ismail ,  Richard H. Tan

IPC: G06F1/20 ,  G06F1/32

Abstract: Systems and methods are disclosed for determining a current machine state of a processing device, predicting a future processing task to be performed by the processing device at a future time, and predicting a list of intervening processing tasks to be performed by a first time (e.g. a current time) and the start of the future processing task. The future processing task has an associated initial state. A feed-forward thermal prediction model determines a predicted future machine state at the time for starting the future processing task. Heat mitigation processes can be applied in advance of the starting of the future processing task, to meet the future initial machine state for starting the future processing task.

Abstract translation: 公开了用于确定处理装置的当前机器状态的系统和方法，预测未来处理装置将来执行的未来处理任务，并预测第一次执行的中间处理任务列表（例如， 当前时间）和未来处理任务的开始。 未来的处理任务具有相关的初始状态。 前馈热预测模型确定在开始未来处理任务时的预测未来机器状态。 可以在未来的处理任务开始之前应用减热过程，以满足未来开始未来处理任务的初始机状态。

公开(公告)号：US11809256B2

公开(公告)日：2023-11-07

申请号：US17521567

申请日：2021-11-08

Applicant: Apple Inc.

Inventor： James S. Ismail ,  Bryan R. Hinch ,  Evan M. Hoke ,  Andrei Dorofeev ,  Shirin Dadashi ,  Mohsen Heidarinejad ,  Reza Arastoo

IPC: G06F1/3228 ,  G06F1/3215 ,  G06F1/20

CPC classification number: G06F1/3228 ,  G06F1/206 ,  G06F1/3215

Abstract: Embodiments are presented herein of, inter alia, systems, devices, and associated methods for allocating and distributing power management budgets for classes of tasks being executed by a computer system, based on thermal feedback loops. Specifically, multiple quality-of-service (QoS) tiers may be defined, and each QoS tier may be allocated power based on a different set of thermal feedback loops. QoS tiers including tasks that are invisible to the user may be mitigated more aggressively than QoS tiers including tasks that are visibly supporting user operations.

公开(公告)号：US11579934B2

公开(公告)日：2023-02-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US11513585B1

公开(公告)日：2022-11-29

申请号：US17221076

申请日：2021-04-02

Applicant: Apple Inc.

Inventor： Patrick Y. Law ,  Robert A. Drebin ,  Keith Cox ,  James S. Ismail

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3218 ,  G06F1/324

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

公开(公告)号：US09128721B2

公开(公告)日：2015-09-08

申请号：US13913307

申请日：2013-06-07

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  James S. Ismail ,  Keith Cox ,  Gaurav Kapoor

IPC: G06F1/24 ,  G06F1/32 ,  G06F1/26

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。