公开(公告)号：US11929129B2

公开(公告)日：2024-03-12

申请号：US17584711

申请日：2022-01-26

Applicant: Arm Limited

Inventor： David Victor Pietromonaco

IPC: H03K5/00 ,  G11C19/28 ,  H03K5/24 ,  H03K19/20

CPC classification number: G11C19/28 ,  H03K5/24 ,  H03K19/20

Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

公开(公告)号：US20230317717A1

公开(公告)日：2023-10-05

申请号：US17708915

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Amit Chhabra ,  Brian Tracy Cline ,  David Victor Pietromonaco

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H03K19/20 ,  G11C11/412

CPC classification number: H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/0665 ,  H03K19/20 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having a multi-device stack structure for use in multi-layered circuit architectures. The multi-device stack structure may have P-type transistors and N-type transistors that are arranged vertically in a multi-transistor stack configuration. In some implementations, the device may have a multi-device stack structure for use in multi-bit memory and/or logic architecture that is formed with complementary field effect transistor (CFET) technology.

公开(公告)号：US20220199629A1

公开(公告)日：2022-06-23

申请号：US17125683

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238

Abstract: Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

公开(公告)号：US12040232B2

公开(公告)日：2024-07-16

申请号：US17980345

申请日：2022-11-03

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092

Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

公开(公告)号：US12035517B2

公开(公告)日：2024-07-09

申请号：US17125683

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H10B10/00 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/06 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0922

Abstract: Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.

公开(公告)号：US20230238072A1

公开(公告)日：2023-07-27

申请号：US17584711

申请日：2022-01-26

Applicant: Arm Limited

Inventor： David Victor Pietromonaco

IPC: G11C19/28 ,  H03K5/24 ,  H03K19/20

CPC classification number: G11C19/28 ,  H03K5/24 ,  H03K19/20

Abstract: In one implementation, a circuit includes: a comparator; a shift register chain coupled to the comparator; and one or more converters coupled to respective shift registers of the shift register chain, wherein the one or more converters are configured to convert a source of current from a first voltage to a second voltage, and wherein the circuit is configured to selectively transmit an output signal to the one or more converters. In one implementation, the circuit is configured to selectively control modulation for the one or more converters.

公开(公告)号：US20230118510A1

公开(公告)日：2023-04-20

申请号：US17980345

申请日：2022-11-03

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H01L21/822 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092

Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.

公开(公告)号：US11128204B2

公开(公告)日：2021-09-21

申请号：US16684449

申请日：2019-11-14

Applicant: Arm Limited

Inventor： David Victor Pietromonaco

IPC: H02K15/00 ,  H02K15/02 ,  H02K3/52 ,  H02K1/08 ,  H02K1/14 ,  H02P25/18 ,  H02K19/06 ,  H02K11/30 ,  H02K1/18 ,  H02K3/28

Abstract: An electric motor is disclosed having a detachable stator tooth. In some implementations, coil windings of the electric motor may be coupled to one or more drivers independently of other coil windings. A method of repairing and manufacturing an electric motor having a detachable stator tooth is also disclosed.

公开(公告)号：US20230062482A1

公开(公告)日：2023-03-02

申请号：US17798518

申请日：2021-02-08

Applicant: Arm Limited

Inventor： Divya Madapusi Srinivas Prasad ,  David Victor Pietromonaco ,  Brian Tracy Cline

IPC: G06F30/367

Abstract: According to one implementation of the present disclosure, a method includes providing one or more tuning parameters of a transistor device at a first temperature of a range of temperatures below a temperature threshold; and adjusting the one or more tuning parameters until one or more second parameters of the transistor device corresponds to substantially the same value at the first temperature as a second temperature above the temperature threshold.

公开(公告)号：US11495499B2

公开(公告)日：2022-11-08

申请号：US17125700

申请日：2020-12-17

Applicant: Arm Limited

Inventor： Amit Chhabra ,  David Victor Pietromonaco

IPC: H01L21/8228 ,  H01L21/822 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092

Abstract: Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.