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    FIN FORMATION BY EPITAXIAL DEPOSITION
    1.
    发明申请
    FIN FORMATION BY EPITAXIAL DEPOSITION 有权
    通过外来沉积形成的FIN形成

    公开(公告)号：US20150050800A1

    公开(公告)日：2015-02-19

    申请号：US14269417

    申请日：2014-05-05

    Applicant: Applied Materials, Inc.

    Inventor： Adam Brand ,  Bingxi Wood ,  Errol Sanchez ,  Yihwan Kim ,  Yi-Chiau Huang ,  John Boland

    IPC: H01L21/02 ,  H01L29/66

    CPC classification number: H01L21/0262 ,  H01L29/66795

    Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

    Abstract translation: 描述形成场效应晶体管的鳍结构的方法。 所述方法可以包括将芯棒图案化在衬底的表面上，以及在图案化心轴的暴露表面上沉积高迁移率沟道材料外延层的操作。 外延层在图案化心轴的相邻列之间留下间隙，并且介电材料可以沉积在图案化心轴的相邻列之间的间隙中。 所述方法还可以包括平坦化外延层以形成平坦化的外延层并暴露图案化心轴的列，以及蚀刻图案化心轴和电介质材料的暴露的柱的至少一部分，以暴露出至少一部分 形成翅片结构的平坦化外延层。

    Forming multiple gate length transistor gates using sidewall spacers
    2.
    发明申请
    Forming multiple gate length transistor gates using sidewall spacers 审中-公开
    使用侧壁间隔件形成多个栅极长度晶体管栅极

    公开(公告)号：US20150031207A1

    公开(公告)日：2015-01-29

    申请号：US14121021

    申请日：2014-07-18

    Applicant: Applied Materials, Inc.

    Inventor： Chris Bencher ,  Adam Brand

    IPC: H01L21/308 ,  H01L21/28

    CPC classification number: H01L21/0337 ,  H01L21/28123 ,  H01L21/32139

    Abstract: A method of fabricating multiple gate lengths simultaneously on a single chip surface. Hard masking materials which are used as spacers in a field effects transistor generation process are converted into a spacer mask to increase the line density on the chip surface. These hard masking spacers are further patterned by either trimming or by enlarging a portion of a spacer at various locations on a chip surface, to enable formation of multiple gate lengths on a single chip, using a series of process steps which make use of combinations of hydrophobic and hydrophilic materials.

    Abstract translation: 在单个芯片表面上同时制造多个栅极长度的方法。 在场效应晶体管生成过程中用作间隔物的硬掩模材料被转换成间隔掩模以增加芯片表面上的线密度。 这些硬掩蔽间隔物通过在芯片表面上的各个位置进行修整或扩大间隔物的一部分进一步图案化，以使得能够在单个芯片上形成多个栅极长度，使用一系列工艺步骤，其使用 疏水和亲水的材料。

    Dual gate process
    6.
    发明授权
    Dual gate process 有权
    双门过程

    公开(公告)号：US08999829B2

    公开(公告)日：2015-04-07

    申请号：US14016865

    申请日：2013-09-03

    Applicant: Applied Materials, Inc.

    Inventor： Adam Brand ,  Bingxi Wood

    IPC: H01L21/3205 ,  H01L29/76 ,  H01L29/49

    CPC classification number: H01L29/49 ,  H01L21/82385 ,  H01L21/823857

    Abstract: The control of gate widths is improved for system-on-a-chip (SoC) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step). The patterned substrate is then processed to selectively deposit a second thickness of gate material. The thin gate may be silicon oxide and the physical thickness of the thin gate may be less than that of the thick gate. In a preferred embodiment, the substrate is not exposed to air or atmosphere after the hardmask is removed.

    Abstract translation: 对于需要多栅极电介质“栅极”厚度的片上系统（SoC）器件，栅极宽度的控制得到改善，例如在同一芯片上进行模拟和数字处理。 形成硬掩模以保护厚栅极，同时蚀刻薄栅区域以去除氧化物（有时称为预清洗步骤）。 然后处理图案化的衬底以选择性地沉积第二厚度的栅极材料。 薄栅极可以是氧化硅，并且薄栅极的物理厚度可以小于厚栅极的物理厚度。 在优选的实施方案中，在去除硬掩模之后，基材不暴露于空气或大气中。

    Fin formation by epitaxial deposition
    7.
    发明授权
    Fin formation by epitaxial deposition 有权
    通过外延沉积形成翅片

    公开(公告)号：US08999821B2

    公开(公告)日：2015-04-07

    申请号：US14269417

    申请日：2014-05-05

    Applicant: Applied Materials, Inc.

    Inventor： Adam Brand ,  Bingxi Wood ,  Errol Sanchez ,  Yihwan Kim ,  Yi-Chiau Huang ,  John Boland

    IPC: H01L21/20 ,  H01L21/02 ,  H01L29/66

    CPC classification number: H01L21/0262 ,  H01L29/66795

    Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

    Abstract translation: 描述形成场效应晶体管的鳍结构的方法。 所述方法可以包括将芯棒图案化在衬底的表面上，以及在图案化心轴的暴露表面上沉积高迁移率沟道材料外延层的操作。 外延层在图案化心轴的相邻列之间留下间隙，并且介电材料可以沉积在图案化心轴的相邻列之间的间隙中。 所述方法还可以包括平坦化外延层以形成平坦化的外延层并暴露图案化心轴的列，以及蚀刻图案化心轴和电介质材料的暴露的柱的至少一部分，以暴露出至少一部分 形成翅片结构的平坦化外延层。

    DUAL GATE PROCESS
    9.
    发明申请
    DUAL GATE PROCESS 有权
    双门过程

    公开(公告)号：US20140113442A1

    公开(公告)日：2014-04-24

    申请号：US14016865

    申请日：2013-09-03

    Applicant: Applied Materials, Inc.

    Inventor： Adam Brand ,  Bingxi Wood

    IPC: H01L29/49

    CPC classification number: H01L29/49 ,  H01L21/82385 ,  H01L21/823857

    Abstract: The control of gate widths is improved for system-on-a-chip (SoC) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step). The patterned substrate is then processed to selectively deposit a second thickness of gate material. The thin gate may be silicon oxide and the physical thickness of the thin gate may be less than that of the thick gate. In a preferred embodiment, the substrate is not exposed to air or atmosphere after the hardmask is removed.

    Abstract translation: 对于需要多栅极电介质“栅极”厚度的片上系统（SoC）器件，栅极宽度的控制得到改善，例如在同一芯片上进行模拟和数字处理。 形成硬掩模以保护厚栅极，同时蚀刻薄栅区域以去除氧化物（有时称为预清洗步骤）。 然后处理图案化的衬底以选择性地沉积第二厚度的栅极材料。 薄栅极可以是氧化硅，并且薄栅极的物理厚度可以小于厚栅极的物理厚度。 在优选的实施方案中，在去除硬掩模之后，基材不暴露于空气或大气中。

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