公开(公告)号：US09703354B2

公开(公告)日：2017-07-11

申请号：US15049236

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

公开(公告)号：US09383806B2

公开(公告)日：2016-07-05

申请号：US13864723

申请日：2013-04-17

Applicant: Apple Inc.

Inventor： Wei-Han Lien ,  Gerard R Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

公开(公告)号：US20150198966A1

公开(公告)日：2015-07-16

申请号：US14153296

申请日：2014-01-13

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Wei-Han Lien ,  Shih-Chieh R. Wen

IPC: G06F1/08 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: A system for managing a change in a frequency of a clock signal, including a clock generator configured to output the clock signal, a clock divider coupled to the output of the clock generator, a processor configured to select the frequency of the clock signal, and a clock management circuit. The clock management circuit may be configured to set the clock generator to adjust the clock signal to the selected frequency. The clock management circuit may be further configured to adjust a divisor value of the clock divider in a plurality of steps in response to a determination the clock signal stabilized at the selected frequency. A new divisor value may be selected during each step in the plurality of steps and each step may occur after a given time period.

Abstract translation: 一种用于管理时钟信号频率变化的系统，包括被配置为输出时钟信号的时钟发生器，耦合到时钟发生器的输出的时钟分配器，被配置为选择时钟信号的频率的处理器，以及 一个时钟管理电路。 时钟管理电路可以被配置为设置时钟发生器以将时钟信号调整到所选择的频率。 时钟管理电路还可以被配置为响应于以所选频率稳定的时钟信号的确定，在多个步骤中调整时钟分频器的除数值。 可以在多个步骤中的每个步骤期间选择新的除数值，并且每个步骤可以在给定时间段之后发生。

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US20230244494A1

公开(公告)日：2023-08-03

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/30196 ,  G06F9/30058

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

公开(公告)号：US09626185B2

公开(公告)日：2017-04-18

申请号：US13774093

申请日：2013-02-22

Applicant: Apple Inc.

Inventor： Shyam Sundar ,  Ian D. Kountanis ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Wei-Han Lien ,  Ramesh B. Gunna

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/30054 ,  G06F9/30181 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844

Abstract: Various techniques for processing and pre-decoding branches within an IT instruction block. Instructions are fetched and cached in an instruction cache, and pre-decode bits are generated to indicate the presence of an IT instruction and the likely boundaries of the IT instruction block. If an unconditional branch is detected within the likely boundaries of an IT instruction block, the unconditional branch is treated as if it were a conditional branch. The unconditional branch is sent to the branch direction predictor and the predictor generates a branch direction prediction for the unconditional branch.

公开(公告)号：US20160055000A1

公开(公告)日：2016-02-25

申请号：US14842915

申请日：2015-09-02

Applicant: APPLE INC.

Inventor： Wei-Han Lien

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3012 ,  G06F9/30123

Abstract: A processor may include a physical register file and a register renamer. The register renamer may be organized into even and odd banks of entries, where each entry stores an identifier of a physical register. The register renamer may be indexed by a register number of an architected register, such that the renamer maps a particular architected register to a corresponding physical register. Individual entries of the renamer may correspond to architected register aliases of a given size. Renaming aliases that are larger than the given size may involve accessing multiple entries of the renamer, while renaming aliases that are smaller than the given size may involve accessing a single renamer entry.

Abstract translation: 处理器可以包括物理寄存器文件和寄存器重命名器。 寄存器重命名器可以被组织成偶数和奇数条目，其中每个条目存储物理寄存器的标识符。 寄存器重命名器可以由架构的寄存器的寄存器编号索引，使得重命名器将特定的架构寄存器映射到相应的物理寄存器。 重命名的个体条目可以对应于给定大小的架构的寄存器别名。 重命名大于给定大小的别名可能涉及访问重命名的多个条目，而重命名小于给定大小的别名可能涉及访问单个重命名条目。

公开(公告)号：US20150236705A1

公开(公告)日：2015-08-20

申请号：US14180976

申请日：2014-02-14

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Shih-Chieh R. Wen ,  Toshinari Takayanagi ,  Wei-Han Lien

IPC: H03L7/08 ,  H03K5/00

CPC classification number: H03L7/08 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  H03K5/00006 ,  H03L7/10 ,  H03L2207/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.

Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。

公开(公告)号：US20140365798A1

公开(公告)日：2014-12-11

申请号：US13910584

申请日：2013-06-05

Applicant: Apple Inc.

Inventor： Shih-Chieh R. Wen ,  Jason M. Kassoff ,  Wei-Han Lien

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/3275 ,  G06F1/3278 ,  Y02D10/14 ,  Y02D10/157

Abstract: A system and a method which include one or more processors, a memory coupled to at least one of the processors, a communication link coupled to the memory, and a power management unit. The power management unit may be configured to detect an inactive state of at least one of the processors. The power management unit may be configured to disable the communication link at a time after the processor enters the inactive state, and disable the memory at another time after the processor enters the inactive state.

Abstract translation: 包括一个或多个处理器，耦合到至少一个处理器的存储器，耦合到存储器的通信链路和电源管理单元的系统和方法。 电源管理单元可以被配置为检测至少一个处理器的不活动状态。 电源管理单元可以被配置为在处理器进入非活动状态之后的一个时间禁用通信链路，并且在处理器进入非活动状态之后的另一时间禁用该存储器。

公开(公告)号：US12067399B2

公开(公告)日：2024-08-20

申请号：US17590719

申请日：2022-02-01

Applicant: Apple Inc.

Inventor： Ian D Kountanis ,  Douglas C Holman ,  Wei-Han Lien ,  Pruthivi Vuyyuru ,  Ethan R Schuchman ,  Niket K Choudhary ,  Kulin N Kothari ,  Haoyan Jia

IPC: G06F9/38

CPC classification number: G06F9/3848 ,  G06F9/3806 ,  G06F9/3844

Abstract: A processor may include a bias prediction circuit and an instruction prediction circuit to provide respective predictions for a conditional instruction. The bias prediction circuit may provide a bias prediction whether a condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction whether the condition of the conditional instruction is true of false. Responsive to a bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.