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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20100230815A1

    公开(公告)日：2010-09-16

    申请号：US12785618

    申请日：2010-05-24

    Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

    Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

    IPC: H01L23/522 ,  H01L23/48

    CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.

    Abstract translation: 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

    Via structure and process for forming the same
    3.
    发明授权
    Via structure and process for forming the same 有权
    通过结构及其形成方法

    公开(公告)号：US07417321B2

    公开(公告)日：2008-08-26

    申请号：US11323484

    申请日：2005-12-30

    Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

    Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Ying-Jing Lu ,  Yu-Sheng Wang ,  Yu-Ku Lin

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Via structure and process flow for interconnection in a semiconductor product. A bottom metal layer is provided to represent a connection layer in the semiconductor product. An isolation layer on the bottom metal layer comprises a via hole exposing a portion of the bottom metal layer. The via hole comprises a sidewall and a bottom. A first barrier metal layer is disposed on the sidewall of the via hole, but not on the bottom of the via hole. A metal under-layer is formed on the bottom of the via hole and on the first barrier metal layer. A second barrier metal layer is formed on the metal under-layer. A metal fill layer fills the via hole. A lattice mismatch between the metal under-layer and the second barrier metal layer is less than about 5%.

    Abstract translation: 通过半导体产品互连的结构和工艺流程。 提供底部金属层以表示半导体产品中的连接层。 底部金属层上的隔离层包括露出底部金属层的一部分的通孔。 通孔包括侧壁和底部。 第一阻挡金属层设置在通孔的侧壁上，但不设置在通孔的底部。 在通孔的底部和第一阻挡金属层上形成金属底层。 在金属底层上形成第二阻挡金属层。 金属填充层填充通孔。 金属底层和第二阻挡金属层之间的晶格失配小于约5％。

    Metal-oxide-metal structure with improved capacitive coupling area
    4.
    发明申请
    Metal-oxide-metal structure with improved capacitive coupling area 审中-公开
    具有改善电容耦合面积的金属氧化物 - 金属结构

    公开(公告)号：US20080061343A1

    公开(公告)日：2008-03-13

    申请号：US11518470

    申请日：2006-09-08

    Applicant: Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    Inventor： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC: H01L29/94

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

    Abstract translation: 一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

    Plating apparatuses and processes
    6.
    发明申请
    Plating apparatuses and processes 审中-公开
    电镀设备和工艺

    公开(公告)号：US20070084730A1

    公开(公告)日：2007-04-19

    申请号：US11248176

    申请日：2005-10-13

    Applicant: Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    Inventor： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC: C25D5/48

    CPC classification number: C25D21/00 ,  C25D5/00 ,  C25D7/123 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

    Abstract: Plating apparatuses and plating processes. Plating apparatuses includes a plating station and a post plating treatment station adjacent to the plating station. The plating station comprises at least one plating cell and provides a first environment therein with a first relative humidity (RH) higher than that of a clean room where the plating apparatus is disposed. The post plating treatment station provides a second environment therein with a second RH lower than the first RH.

    Abstract translation: 电镀设备和电镀工艺。 电镀装置包括电镀站和邻近电镀站的电镀后处理站。 电镀站包括至少一个电镀槽，并在其中提供第一相对湿度（RH）高于设置有电镀设备的洁净室的第一相对湿度（RH）。 后电镀处理站在其中提供第二环境，其第二RH低于第一RH。

    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    7.
    发明授权
    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
    在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法

    公开(公告)号：US07071100B2

    公开(公告)日：2006-07-04

    申请号：US10788912

    申请日：2004-02-27

    Applicant: Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    Inventor： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC: H01L21/4763

    CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

    Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

    Abstract translation: 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

    Copper plating of semiconductor devices using intermediate immersion step
    8.
    发明申请
    Copper plating of semiconductor devices using intermediate immersion step 有权
    使用中间浸渍步骤的半导体器件的镀铜

    公开(公告)号：US20050250327A1

    公开(公告)日：2005-11-10

    申请号：US10840095

    申请日：2004-05-06

    Applicant: Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    Inventor： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

    IPC: C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  C25D7/12 ,  H01L21/288 ,  H01L21/44

    CPC classification number: C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

    Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

    Abstract translation: 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    9.
    发明申请
    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
    在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法

    公开(公告)号：US20050191855A1

    公开(公告)日：2005-09-01

    申请号：US10788912

    申请日：2004-02-27

    Applicant: Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    Inventor： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC: H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

    Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

    Abstract translation: 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

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