公开(公告)号：US07028135B2

公开(公告)日：2006-04-11

申请号：US10229924

申请日：2002-08-28

Applicant: Pietro Piersimoni ,  Pasquale Pistilli ,  Elio D'Ambrosio

Inventor： Pietro Piersimoni ,  Pasquale Pistilli ,  Elio D'Ambrosio

IPC: G06F12/00

CPC classification number: G11C16/06

Abstract: A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.

公开(公告)号：US20050280072A1

公开(公告)日：2005-12-22

申请号：US11216263

申请日：2005-08-31

Applicant: Giovanni Naso ,  Elio D'Ambrosio

Inventor： Giovanni Naso ,  Elio D'Ambrosio

IPC: G11C29/14 ,  G11C29/46 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105 ,  H01L29/76

CPC classification number: G11C29/46 ,  G11C16/04 ,  G11C29/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

公开(公告)号：US07995365B1

公开(公告)日：2011-08-09

申请号：US12434600

申请日：2009-05-01

Applicant: Elio D'Ambrosio ,  Ciro Chiacchio ,  Dionisio Minopoli

Inventor： Elio D'Ambrosio ,  Ciro Chiacchio ,  Dionisio Minopoli

IPC: G11C5/00 ,  G11C7/00

CPC classification number: G11C7/1066

Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.

Abstract translation: 这里描述了用于提供DDR存储器访问的方法和装置。 在一个实施例中，一种装置包括用于存储和同步多条数据线信号与时钟信号的数据存储单元。 该装置包括：接收多条数据线信号并选择两条数据线信号的选择器单元。 该装置还包括双数据速率（DDR）输出单元，其接收来自选择器单元的两条数据线信号，并产生具有大约时钟信号时钟周期的一半的时间周期的DDR数据线信号。 该装置还包括耦合到DDR输出单元并且相对于DDR输出单元本地定位的输入/输出（I / O）焊盘。 数据存储单元，选择器单元和DDR输出单元组合形成I / O缓冲器，其本地耦合到I / O焊盘。

公开(公告)号：US07057416B2

公开(公告)日：2006-06-06

申请号：US11003676

申请日：2004-12-03

Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

IPC: H03K19/175

CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

公开(公告)号：US06981237B2

公开(公告)日：2005-12-27

申请号：US10703322

申请日：2003-11-07

Applicant: Pasquale Pistilli ,  Elio D'Ambrosio

Inventor： Pasquale Pistilli ,  Elio D'Ambrosio

IPC: G06F17/50 ,  G11C17/12 ,  G11C17/18 ,  H03K19/082 ,  H03K19/084

CPC classification number: G11C17/10 ,  G11C17/12 ,  G11C17/18

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

公开(公告)号：US06977410B2

公开(公告)日：2005-12-20

申请号：US10880894

申请日：2004-06-30

Applicant: Giovanni Naso ,  Elio D'Ambrosio

Inventor： Giovanni Naso ,  Elio D'Ambrosio

IPC: G11C29/14 ,  G11C29/46 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105 ,  H01L29/76 ,  H01L29/788

CPC classification number: G11C29/46 ,  G11C16/04 ,  G11C29/14 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

Abstract translation: 本发明的实施例包括将集成电路放入测试模式的接口电路和解码器来解码提供给集成电路的一个或多个命令。 解码器包括子电路，并且每个子电路具有串联耦合的多个晶体管。 串联耦合的晶体管具有耦合到时钟信号的控制栅极或表示命令的几个反相或非反相命令信号之一。 每个子电路中的控制栅极被耦合，使得时钟信号和命令信号的独特模式将导通所有晶体管以解码该命令。 每个子电路能够解码单个命令。 子电路具有比p沟道晶体管更多的n沟道晶体管的逻辑比。 解码器可以通过通孔的灵活放置来制造。

公开(公告)号：US06920626B2

公开(公告)日：2005-07-19

申请号：US10703898

申请日：2003-11-07

Applicant: Pasquale Pistilli ,  Elio D'Ambrosio

Inventor： Pasquale Pistilli ,  Elio D'Ambrosio

IPC: G06F17/50 ,  G11C17/12 ,  G11C17/18 ,  H03K19/082 ,  H03K19/084

CPC classification number: G11C17/10 ,  G11C17/12 ,  G11C17/18

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract translation: 具有通过掩码可编程性的命令用户界面包括具有可选择地与输入或其补码之一相连的晶体管的解码器。 这通过在合适的位置形成通孔以允许适当的接触和晶体管的栅极互连来实现。

公开(公告)号：US06628142B1

公开(公告)日：2003-09-30

申请号：US09651478

申请日：2000-08-30

Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

IPC: H03K19175

CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

Abstract translation: 讨论了抑制低压集成电路中的薄栅氧化物晶体管的半导体击穿的输入缓冲器。 输入缓冲器的一个方面包括具有栅极，漏极和源极的输入级。 输入级的门接受禁止信号，漏极接受输入信号。 当禁止信号处于预定电平时，输入级禁止在输入级的源处呈现输入信号。 输入缓冲器还包括具有包括第一连接和第二连接的逆变器的输出级。 第一连接耦合到输入级的源极，第二连接将输入信号提供给低压闪存器件。

公开(公告)号：US20060077078A1

公开(公告)日：2006-04-13

申请号：US11288471

申请日：2005-11-29

Applicant: Pasquale Pistilli ,  Elio D'Ambrosio

Inventor： Pasquale Pistilli ,  Elio D'Ambrosio

IPC: H03M7/00

CPC classification number: G11C17/10 ,  G11C17/12 ,  G11C17/18

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

公开(公告)号：US06949957B2

公开(公告)日：2005-09-27

申请号：US10703880

申请日：2003-11-07

Applicant: Pasquale Pistilli ,  Elio D'Ambrosio

Inventor： Pasquale Pistilli ,  Elio D'Ambrosio

IPC: G06F17/50 ,  G11C17/12 ,  G11C17/18 ,  H03K19/082 ,  H03K19/084

CPC classification number: G11C17/10 ,  G11C17/12 ,  G11C17/18

Abstract: A command user interface with via mask programmability includes a decoder with transistors selectively coupleable to one of an input or its complement. This is accomplished in one way by making vias in an appropriate location to allow interconnection of the appropriate contact and the gate of the transistor.

Abstract translation: 具有通过掩码可编程性的命令用户界面包括具有可选择地与输入或其补码之一相连的晶体管的解码器。 这通过在合适的位置形成通孔以允许适当的接触和晶体管的栅极互连来实现。