公开(公告)号：US20250070071A1

公开(公告)日：2025-02-27

申请号：US18810723

申请日：2024-08-21

Applicant: LAPIS Technology Co., Ltd.

Inventor： Daisuke TAKAGI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L25/065

Abstract: A semiconductor device including: a semiconductor chip including redistribution wiring; a lead frame including a die pad mounted with the semiconductor chip and a lead connected to the die pad, wherein the redistribution wiring and the die pad are electrically connected by a solder or a conductive adhesive; and a sealing member that seals the semiconductor chip.

公开(公告)号：US20250070000A1

公开(公告)日：2025-02-27

申请号：US18943461

申请日：2024-11-11

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio FONTANA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

公开(公告)号：US20250069997A1

公开(公告)日：2025-02-27

申请号：US18945218

申请日：2024-11-12

Applicant: ROHM CO., LTD.

Inventor： Kazuki OKUYAMA ,  Shuntaro TAKAHASHI ,  Motoharu HAGA ,  Shingo YOSHIDA ,  Kazuhisa KUMAGAI ,  Hajime OKUDA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/765 ,  H01L23/00 ,  H01L23/31 ,  H01L23/34 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.

公开(公告)号：US20250069974A1

公开(公告)日：2025-02-27

申请号：US18470730

申请日：2023-09-20

Applicant: PANJIT INTERNATIONAL INC.

Inventor： CHUNG-HSIUNG HO ,  JENG-SIAN WU

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

Abstract: A wafer level packaging component having a side wettable structure includes a substrate, a function area, a first protective layer, and a redistribution layer (RDL). Half cut grooves are respectively formed on two opposite sides of the substrate. The function area is covered in the substrate, and has conductive pads exposed from a top surface of the substrate. The first protective layer is mounted on the top surface of the substrate, and has openings to expose the conductive pads. The RDL is mounted on the first protective layer, and has redistribution circuits to connect the conductive pads and to extend to the half cut grooves. Since dies are not needed to be cut before packaging the dies, there is no need to process the die bonding process, the molding process, and the grinding process. Processes of manufacturing can be improved, and cost of manufacturing can be decreased.

公开(公告)号：US20250069954A1

公开(公告)日：2025-02-27

申请号：US18948999

申请日：2024-11-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/78 ,  B23K26/40 ,  B23K103/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

公开(公告)号：US12238865B2

公开(公告)日：2025-02-25

申请号：US17706037

申请日：2022-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jui-Pin Hung ,  Kuo-Chung Yee

IPC: H05K1/18 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H05K3/30 ,  H05K3/34

Abstract: An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.

公开(公告)号：US12237305B2

公开(公告)日：2025-02-25

申请号：US17958298

申请日：2022-09-30

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L25/00 ,  H01L25/07

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US12237291B2

公开(公告)日：2025-02-25

申请号：US17843725

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Hui Cheng ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

公开(公告)号：US12237245B2

公开(公告)日：2025-02-25

申请号：US18089207

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/18

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US12237241B2

公开(公告)日：2025-02-25

申请号：US17718662

申请日：2022-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yanggyoo Jung ,  Seungbin Baek ,  Hyunjung Song ,  Jisun Yang

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a package substrate; an interposer disposed on the package substrate; a first semiconductor chip mounted on the interposer; a second semiconductor chip mounted on the interposer adjacent to the first semiconductor chip, the second semiconductor chip having an overhang portion that does not overlap the interposer in a vertical direction; a first underfill disposed between the package substrate and the interposer, the first underfill having a first extension portion extending from a side surface of the interposer; a second underfill disposed between the interposer and the second semiconductor chip, the second underfill having a second extension portion extending to an upper surface of the package substrate along at least a portion of the first extension portion of the first underfill, wherein the second extension portion protrudes from the overhang portion contact the upper surface of the package substrate.