公开(公告)号：US20120305943A1

公开(公告)日：2012-12-06

申请号：US13485423

申请日：2012-05-31

申请人： Misako HONAGA ,  Takeyoshi MASUDA ,  Keiji WADA ,  Toru HIYOSHI

发明人： Misako HONAGA ,  Takeyoshi MASUDA ,  Keiji WADA ,  Toru HIYOSHI

IPC分类号： H01L29/161 ,  H01L21/334

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068

摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j

摘要翻译： 漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。 身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

公开(公告)号：US08268695B2

公开(公告)日：2012-09-18

申请号：US12190821

申请日：2008-08-13

申请人： Mark Kiehlbauch ,  Kevin R. Shea

发明人： Mark Kiehlbauch ,  Kevin R. Shea

IPC分类号： H01L21/20 ,  H01L21/31 ,  H01L21/469 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852

摘要： Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.

摘要翻译： 一些实施例包括使用含碳支撑材料制造螺柱型电容器的方法。 开口可以通过含碳支撑材料形成到电节点，并且随后可以在开口内生长导电材料。 然后可以除去含碳支撑材料，并且将导电材料用作螺柱式电容器的螺柱式存储节点。 螺柱式电容器可以并入到DRAM中，并且可以在电子系统中使用DRAM。

公开(公告)号：US07932154B2

公开(公告)日：2011-04-26

申请号：US12007097

申请日：2008-01-07

申请人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

发明人： Sang-Su Kim ,  Sung-Taeg Kang ,  In-Wook Cho ,  Jeong-Hwan Yang

IPC分类号： H01L21/334

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.

摘要翻译： 在非易失性闪速存储器件及其制造方法中，该器件包括半导体衬底，设置在半导体衬底中的源极区和漏极区以彼此间隔开，隧道层图案， 电荷陷阱层图案和屏蔽层图案，它们在与源极区相邻的源极区域和漏极区域之间的半导体衬底上依次层叠，设置在半导体衬底中的在隧道层图案下方的第一沟道区域，栅极 在所述漏极区域和所述第一沟道区域之间设置在所述半导体衬底上的绝缘层，设置在所述半导体衬底中的所述栅极绝缘层下方的第二沟道区域，所述第二沟道区域的浓度与所述第一沟道区域的浓度不同，以及 覆盖屏蔽层图案的栅电极和栅极绝缘层。

公开(公告)号：US20100200949A1

公开(公告)日：2010-08-12

申请号：US12370024

申请日：2009-02-12

申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Robert Hannon ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Robert Hannon ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/334

CPC分类号： H01L29/945 ,  H01L27/0605 ,  H01L27/0733 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/66181

摘要： A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.

摘要翻译： 形成深沟槽电容器的方法包括提供晶片。 器件形成在晶片的前侧。 在晶片的基板上形成贯通硅通孔。 深沟槽形成在晶片的背面。 在深沟槽中形成深沟槽电容器。 直通硅通孔将深沟槽电容器连接到器件。

公开(公告)号：US06979613B1

公开(公告)日：2005-12-27

申请号：US10707027

申请日：2003-11-16

申请人： Kuo-Chien Wu ,  Ping Hsu

发明人： Kuo-Chien Wu ,  Ping Hsu

IPC分类号： H01L21/20 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.

摘要翻译： 一种制造深沟槽电容器的方法。 提供了具有堆叠在其主表面上的衬垫氧化物层和衬垫氮化物层的衬底。 通过衬垫氧化物层和衬垫氮化物层将深沟槽蚀刻到衬底中。 节点电介质涂覆在深沟槽的内表面上。 硅间隔层形成在节点电介质上的深沟槽的侧壁上。 硅间隔层的上部掺杂有诸如BF 2 N的掺杂剂。 选择性地去除硅间隔层的未掺杂部分以暴露节点电介质的一部分。 将暴露的节点电介质剥离以露出衬底。 由掺杂硅间隔层覆盖的剩余节点电介质形成保护间隔物，用于在随后的蚀刻工艺期间保护衬垫氧化物层不受腐蚀。

公开(公告)号：US06977227B2

公开(公告)日：2005-12-20

申请号：US10871619

申请日：2004-06-18

申请人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Yu-Sheng Hsu ,  Chung-Yuan Lee

IPC分类号： H01L21/033 ,  H01L21/20 ,  H01L21/308 ,  H01L21/311 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L29/66181 ,  H01L29/945

摘要： A method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. The invention also discloses a method of fabricating a bottle trench capacitor.

摘要翻译： 一种形成瓶槽的方法。 首先，在进行光刻之前，将由光致抗蚀剂层覆盖的基板旋转到特定角度，从而在光致抗蚀剂层中形成矩形开口并暴露基板，其中矩形开口的边缘基本上平行于{110} 由于基板的旋转而导致基板的平面。 接下来，暴露的衬底被蚀刻以在其中形成沟槽，其中沟槽的侧壁表面是衬底的{110}平面。 最后，使用形成在沟槽的上部的侧壁上的蚀刻屏蔽层作为蚀刻掩模，在沟槽的下部的基板上进行各向同性蚀刻，以形成瓶沟槽。 本发明还公开了一种制造瓶沟电容器的方法。

公开(公告)号：US06972240B2

公开(公告)日：2005-12-06

申请号：US10717286

申请日：2003-11-19

申请人： Patrick Poveda

发明人： Patrick Poveda

IPC分类号： H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L29/66181 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76229

摘要： A method for forming narrow trenches in a silicon substrate, comprising the steps of: etching the substrate to form first trenches separated by first silicon ribs; performing a thermal oxidation of the substrate to form a silicon oxide layer around the substrate, to obtain second trenches and second silicon ribs; filling the second trenches with fingers of an etchable material; etching the oxide down to the upper surface of the second ribs while keeping oxide portions between said material fingers and the second ribs; etching away the second silicon ribs and said material fingers; etching the oxide to expose the substrate at the bottom of the oxide portions, while keeping oxide fingers; and etching the substrate between the oxide fingers to form narrow trenches in the substrate.

摘要翻译： 一种用于在硅衬底中形成窄沟槽的方法，包括以下步骤：蚀刻衬底以形成由第一硅肋分隔开的第一沟槽; 进行基板的热氧化以在基板周围形成氧化硅层，以获得第二沟槽和第二硅肋; 用可蚀刻材料的手指填充第二沟槽; 将氧化物蚀刻到第二肋的上表面，同时保持所述材料指和第二肋之间的氧化物部分; 蚀刻掉第二硅肋和所述材料指; 蚀刻氧化物以在氧化物部分的底部露出衬底，同时保持氧化物指; 并蚀刻氧化物指状物之间的衬底以在衬底中形成窄沟槽。

公开(公告)号：US20050248906A1

公开(公告)日：2005-11-10

申请号：US11167694

申请日：2005-06-27

申请人： Yee-Chia Yeo ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Chenming Hu

IPC分类号： H01G4/228 ,  H01L21/00 ,  H01L21/02 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8239 ,  H01L21/84 ,  H01L27/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L29/92 ,  H01L29/94

CPC分类号： H01L27/0805 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/65 ,  H01L29/66181 ,  H01L29/94 ,  Y10S257/905 ,  Y10S257/908

摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

摘要翻译： 在包括硅表面层的半导体衬底上形成去耦电容器。 在半导体表面层的一部分中形成基本平坦的底部电极。 电容器电介质覆盖在底部电极上。 电容器电介质由具有相对介电常数（优选大于约5）的高介电常数电介质形成。电容器还包括覆盖在电容器电介质上的基本平坦的顶部电极。 在优选的应用中，顶部电极连接到第一参考电压线，底部电极连接到第二参考电压线。

公开(公告)号：US06956259B2

公开(公告)日：2005-10-18

申请号：US10458489

申请日：2003-06-11

申请人： Yasushi Akasaka

发明人： Yasushi Akasaka

IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/336

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semiconductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.

摘要翻译： 公开了一种半导体器件，包括其表面上具有沟槽的半导体衬底，形成在沟槽内的多晶半导体膜，沉积在半导体衬底的表面区域上的扩散层和介于扩散层和 所述多晶半导体膜，所述金属半导体氮化物层包括构成所述半导体衬底的金属，氮和半导体，以及将所述多晶半导体膜与所述扩散层电连接。

公开(公告)号：US06955962B2

公开(公告)日：2005-10-18

申请号：US10697649

申请日：2003-10-31

申请人： David Griffiths

发明人： David Griffiths

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

摘要： A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a portion of the first layer to form a residual first insulating layer, forming a first conductive layer on the residual first layer, removing a portion of the first conductive layer, removing a portion of the residual first layer, driving out charged elements from the first layer into the semiconductor substrate, to form a first doped substrate region, removing the first layer, forming a node nitride on the trench, forming a second conductive layer on the pad layer and on the trench, removing a portion of the second conductive layer to form a second doped substrate region in the trench.

摘要翻译： 一种制造存储单元的沟槽电容器的方法，包括：提供具有由衬垫层覆盖的表面的半导体衬底，在衬底中形成沟槽，在焊盘层和沟槽表面上形成第一层，去除 所述第一层的一部分形成残留的第一绝缘层，在所述残留的第一层上形成第一导电层，去除所述第一导电层的一部分，去除所述残留的第一层的一部分， 层以形成第一掺杂衬底区域，去除第一层，在沟槽上形成节点氮化物，在焊盘层和沟槽上形成第二导电层，将第二导电层的一部分去除 在沟槽中形成第二掺杂衬底区域。