公开(公告)号：US20250036839A1

公开(公告)日：2025-01-30

申请号：US18408590

申请日：2024-01-10

Applicant: SK hynix Inc.

Inventor： Jung Hyun KWON ,  Min Seob LEE

IPC: G06F30/3312 ,  G06F30/3947 ,  G06F119/12

Abstract: Disclosed is a semiconductor device and a semiconductor system including the same, the semiconductor device includes a plurality of pads, a data pattern analysis circuit configured to generate analysis signals by analyzing a data pattern of each of data mapped to each of the plurality of pads, a data remapping circuit configured to re-determine a relationship between the data and the plurality of pads based on the analysis signals, and remap the data to the plurality of pads based on the re-determined relationship, and an output circuit configured to output the remapped data through the plurality of pads.

公开(公告)号：US12124782B1

公开(公告)日：2024-10-22

申请号：US17516441

申请日：2021-11-01

Applicant: Synopsys, Inc.

Inventor： Siddhartha Nath ,  Vishal Khandelwal

IPC: G06F30/3312 ,  G06F119/12 ,  G06N5/01

CPC classification number: G06F30/3312 ,  G06N5/01 ,  G06F2119/12

Abstract: A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.

公开(公告)号：US20240303403A1

公开(公告)日：2024-09-12

申请号：US18178976

申请日：2023-03-06

Applicant: Synopsys, Inc.

Inventor： Olivier Coudert ,  Kiran Ramchandra Lokhande ,  Prashant Kumar Mishra

IPC: G06F30/3312 ,  G06F30/392

CPC classification number: G06F30/3312 ,  G06F30/392 ,  G06F2119/12

Abstract: Disclosed are techniques for simulation of a circuit design using a set of primary signals captured by a hardware emulation system. In preparation for simulation, the circuit design is divided into partitions that are substantially uniform in size. Sequential dependencies are then identified based on signals that cross partitions. The set of primary signals includes signals that, when provided as input to the simulation, break the sequential dependencies such that each partition can be simulated independently. Techniques for determining which signals to include in the set of primary signals are also disclosed. The hardware emulation system is configured to capture values of the primary signals as part of emulating the circuit design. Afterwards, the simulation is performed using the captured values. During the simulation, non-primary signals are reconstructed using values obtained from simulating each partition independently.

公开(公告)号：US12039240B2

公开(公告)日：2024-07-16

申请号：US17517322

申请日：2021-11-02

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： Hsing-Han Tseng ,  Yung-Jen Chen ,  Yu-Lan Lo

IPC: G06F30/3312 ,  G06F30/323 ,  G06F30/327 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/323 ,  G06F30/327 ,  G06F2119/12

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

公开(公告)号：US12001768B1

公开(公告)日：2024-06-04

申请号：US17411578

申请日：2021-08-25

Applicant: Synopsys, Inc.

Inventor： Qing Su ,  Pankaj Singla ,  Solaiman Rahim ,  Eduard Petrus Huijbregts ,  Stephan Houben

IPC: G06F30/3312 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/3315 ,  G06F2119/12

Abstract: A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

公开(公告)号：US11983477B2

公开(公告)日：2024-05-14

申请号：US17404977

申请日：2021-08-17

Applicant: International Business Machines Corporation

Inventor： Lakshmi N. Reddy ,  Ying Zhou ,  Cindy S. Washburn ,  Alexander Joel Suess

IPC: G06F30/394 ,  G06F30/3312 ,  G06F30/398

CPC classification number: G06F30/394 ,  G06F30/3312 ,  G06F30/398

Abstract: To increase the efficiency of electronic design automation, at an end point of physical design synthesis optimization flow for a putative integrated circuit design having a plurality of nets, identify at least one congested region in the putative integrated circuit design. Identify those of the nets of the putative integrated circuit design traversing through the at least one congested region, to obtain a plurality of candidate nets for demotion. Demote a plurality of selected nets, selected from the plurality of candidate nets for demotion, from an upper routing layer of the putative integrated circuit design to a lower routing layer of the putative integrated circuit design. At least some of the plurality of selected nets experience a loss of timing quality of result after the demoting.

公开(公告)号：US20240143881A1

公开(公告)日：2024-05-02

申请号：US18358449

申请日：2023-07-25

Applicant: VIETTEL GROUP

Inventor： Thai Ha Le ,  Ha My Bui ,  Anh Tuan Khong

IPC: G06F30/333 ,  G06F30/3312

CPC classification number: G06F30/333 ,  G06F30/3312

Abstract: The present invention discloses a DFT (Design for test) methodology to integrate synchronous double-clock latches to synchronize data transferring between two asynchronous clock domains, where the conventional lockup-latches (asynchronous latches) are automatically inserted to connect/combine the two independent asynchronous DFT chains for a more compacted solution. If the asynchronous latches are replaced by the synchronous double-clock ones, the static timing analysis (STA) will check both ends of the latches, therefore, the full combined chain is safe from the setup-hold issues. This method utilizes the automatic flow of asynchronous latches insertion to connect independent DFT chains. Then these conventional latches are replaced by synchronous ones. Both the synthesis, the physical implementation flows in the DFT design and the automatic-test pattern generation (ATPG) scheme have been modified to match these replacements.

公开(公告)号：US20240143877A1

公开(公告)日：2024-05-02

申请号：US17978002

申请日：2022-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Nikita Sergeev ,  Pradeep Yadav ,  Maksim Baranov

IPC: G06F30/3312 ,  G06F30/31

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Disclosed is an improved approach to implement sharing of delay calculations for replicated portions of a design, where input slews may be different between those replicated design portions. This allows the system to experience runtime improvements for timing analysis of electronic designs.

公开(公告)号：US20240086605A1

公开(公告)日：2024-03-14

申请号：US18518167

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kenan Yu ,  Qingwen Deng

IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/20

Abstract: A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

公开(公告)号：US11907631B2

公开(公告)日：2024-02-20

申请号：US17480574

申请日：2021-09-21

Applicant: Synopsys, Inc.

Inventor： Fahim Rahim ,  Paras Mal Jain ,  Rajarshi Mukherjee ,  Deep Shah ,  Satrajit Pal ,  Dipit Ranjan Senapati ,  Abhishek Kumar

IPC: G06F30/3312 ,  G06F30/31 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.