公开(公告)号：US20170024508A1

公开(公告)日：2017-01-26

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

Abstract translation: 用于管理和组合验证引擎并同时应用这样的组合以用设计约束验证属性的系统和方法基于要检查的属性和可选地用户指定的预算将计算资源分配给验证引擎。 运行验证引擎，以便根据系统接收的用户指定的断言和约束验证电路的接收到的寄存器传输级（RTL）设计描述。 从这样的引擎的数据库中选择要运行的特定验证引擎，并且在顺序，并行和分布式流中指定运行顺序。

公开(公告)号：US20160259879A1

公开(公告)日：2016-09-08

申请号：US14790318

申请日：2015-07-02

Applicant: Synopsys, Inc.

Inventor： Malay Ganai ,  Mohamed Shaker Sarwary ,  Maher Mneimneh ,  Paras Mal Jain ,  Mohammad Homayoun Movahed-Ezazi ,  Pronay Kumar Biswas ,  Nishant Gupta

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/62

Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.

Abstract translation: 网表时域交叉验证的系统和方法利用RTL时钟域交叉（CDC）验证数据和结果。 网表时域交叉验证系统（NCDC）将RTL级别约束和放弃迁移到网表设计，以便用户不必重新输入。 NCDC检查网表，并生成一个报告，将RTL级CDC检查结果与网表级CDC检查结果进行比较，以便轻松查看新问题。 NCDC从网络列表中接收并存储用户输入的网表更正或自动更正某些CDC违规行为。

公开(公告)号：US11467851B1

公开(公告)日：2022-10-11

申请号：US17100625

申请日：2020-11-20

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Rajarshi Mukherjee ,  Paras Mal Jain ,  David L. Allen

IPC: G06F9/445 ,  G06F30/33 ,  G06N20/00 ,  G06F30/20

Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.

公开(公告)号：US11347917B2

公开(公告)日：2022-05-31

申请号：US17316610

申请日：2021-05-10

Applicant: Synopsys, Inc.

Inventor： Deepak Ahuja ,  Anchit Jain ,  Paras Mal Jain

IPC: G06F30/327 ,  G06F30/3312 ,  G06F30/3315 ,  G06F30/396 ,  G06F30/398 ,  G06F119/12 ,  G06F119/02 ,  G06F117/04

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

公开(公告)号：US20160342727A1

公开(公告)日：2016-11-24

申请号：US14716422

申请日：2015-05-19

Applicant: Synopsys, Inc.

Inventor： Mohamed Shaker Sarwary ,  Paras Mal Jain ,  Anshu Malani

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

Abstract: In a method of checking an integrated circuit design prior to running a simulation, a shoot-through RTL Checker reads RTL design files, uses a simulator delta cycle definitions to compute clock delta delays, and helps to correct and report any conditions that are expected will cause the simulation to generate incorrect results, in particular shoot-through conditions at circuit memory elements such as source and destination flip-flops or registers.

Abstract translation: 在运行仿真之前检查集成电路设计的方法中，直通RTL​​检查器读取RTL设计文件，使用模拟器增量循环定义来计算时钟延迟延迟，并帮助纠正和报告任何预期的条件 导致模拟产生不正确的结果，特别是在诸如源和目标触发器或寄存器的电路存储器元件的直通条件。

公开(公告)号：US11907631B2

公开(公告)日：2024-02-20

申请号：US17480574

申请日：2021-09-21

Applicant: Synopsys, Inc.

Inventor： Fahim Rahim ,  Paras Mal Jain ,  Rajarshi Mukherjee ,  Deep Shah ,  Satrajit Pal ,  Dipit Ranjan Senapati ,  Abhishek Kumar

IPC: G06F30/3312 ,  G06F30/31 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/31 ,  G06F2119/12

Abstract: Reset Domain Crossing (RDC) detection and simulation is provided via identifying a plurality of RDCs between flip-flops of a sequence of flip-flops leading to an observation point in a circuit design; classifying each RDC of the plurality of RDCs as one of observable at the observation point or not observable at the observation point based on a reset order applied to the sequence of flip-flops; and outputting a list of the plurality of RDCs classified as observable at the observation point.

公开(公告)号：US20230065867A1

公开(公告)日：2023-03-02

申请号：US17894557

申请日：2022-08-24

Applicant: Synopsys, Inc.

Inventor： Brijesh Agrawal ,  Abhishek Verma ,  Deepak Ahuja ,  Paras Mal Jain

IPC: G06F16/901 ,  G06F30/394

Abstract: Sets of objects may be received which are desired to be stored using a nested hash map, where the nested hash map may include multiple levels, and where each set of objects in the sets of objects may correspond to a level in the nested hash map. The nested hash map may be created from a bottom level of the nested hash map to a top level of the nested hash map, which may include: creating a first hash map at a first level of the nested hash map, creating a first shared pointer which points to the first hash map, and creating a second hash map at a second level which is immediately above the first level, where the second hash map maps at least one object to the first shared pointer.

公开(公告)号：US11238202B2

公开(公告)日：2022-02-01

申请号：US16910953

申请日：2020-06-24

Applicant: Synopsys, Inc.

Inventor： Sudeep Mondal ,  Paras Mal Jain ,  Anshul Tuteja

IPC: G06F30/33 ,  G06F30/3308 ,  G06F30/323 ,  G06F30/3323 ,  G06F119/12

Abstract: A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.

公开(公告)号：US10387605B2

公开(公告)日：2019-08-20

申请号：US14807676

申请日：2015-07-23

Applicant: Synopsys, Inc.

Inventor： Maher Mneimneh ,  Scott Cotton ,  Mohamed Shaker Sarwary ,  Fahim Rahim ,  Sudeep Mondal ,  Paras Mal Jain

IPC: G06F17/50

Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

公开(公告)号：US09721057B2

公开(公告)日：2017-08-01

申请号：US14790318

申请日：2015-07-02

Applicant: Synopsys, Inc.

Inventor： Malay Ganai ,  Mohamed Shaker Sarwary ,  Maher Mneimneh ,  Paras Mal Jain ,  Mohammad Homayoun Movahed-Ezazi ,  Pronay Kumar Biswas ,  Nishant Gupta

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/62

Abstract: A system and method for netlist clock domain crossing verification leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design so that the user does not have to re-enter them. The NCDC checks the netlist and generates a report that compares RTL-level CDC checking results to the netlist-level CDC checking results to make it easy to see new issues. The NCDC receives and stores netlist corrections from user input or automatically corrects certain CDC violations, in the netlist.