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    AUTOMATED COVERAGE CONVERGENCE BY CORRELATING RANDOM VARIABLES WITH COVERAGE VARIABLES SAMPLED FROM SIMULATION RESULT DATA
    1.
    发明申请
    AUTOMATED COVERAGE CONVERGENCE BY CORRELATING RANDOM VARIABLES WITH COVERAGE VARIABLES SAMPLED FROM SIMULATION RESULT DATA 审中-公开

    公开(公告)号：US20200019664A1

    公开(公告)日：2020-01-16

    申请号：US16510810

    申请日：2019-07-12

    Applicant: Synopsys, Inc.

    Inventor： Esha Dutta ,  Danish Jawed ,  Bhaskar Pal ,  Parijat Biswas ,  Pravash Chandra Dash ,  Rajarshi Mukherjee ,  Sharad Gaur

    IPC: G06F17/50

    Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

    ACCURATE GLITCH DETECTION
    2.
    发明申请
    ACCURATE GLITCH DETECTION 有权
    精准玻璃检测

    公开(公告)号：US20170053051A1

    公开(公告)日：2017-02-23

    申请号：US15011546

    申请日：2016-01-30

    Applicant: Synopsys, Inc.

    Inventor： Kaushik De ,  Dipti Ranjan Senapati ,  Mahantesh D. Narwade ,  Namit K. Gupta ,  Rajarshi Mukherjee

    IPC: G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

    Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).

    Abstract translation: 描述了用于检测电路设计中的设计问题的系统和技术。 可以合成电路设计的更高层次的抽象，以获得电路设计的较低级别抽象，以及较高级抽象中的信号与较低级别抽象中的信号之间的映射。 可以在电路设计中检测到设计问题，以响应于当使能信号被分配了阻塞值（确定了使能信号和相应的阻塞值）时，确定下级抽象中的信号中的可能的毛刺不被阻塞 通过分析上级抽象）。

    Minimizing crossover paths for functional verification of a circuit description
    3.
    发明授权
    Minimizing crossover paths for functional verification of a circuit description 有权
    最小化电路描述功能验证的交叉路径

    公开(公告)号：US09529948B2

    公开(公告)日：2016-12-27

    申请号：US14529048

    申请日：2014-10-30

    Applicant: Synopsys, Inc.

    Inventor： Kaushik De ,  Mahantesh Narwade ,  Rajarshi Mukherjee ,  Namit Gupta

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/78

    Abstract: A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors.

    Abstract translation: 一种用于电路描述的功能验证的方法包括基于所述电路描述生成第一组交叉路径，基于与所述电路描述相关联的功率设计描述生成低功率信息，所述低功率信息确定一组功率状态 组合，以及基于所述第一组交叉路径和所述低功率信息生成第二组交叉路径，所述第二组交叉路径是所述第一组交叉路径的子集。 评估第二组交叉路径中的每一个以识别电路描述错误，特别是功能电路描述错误。

    Machine learning (ML)-based static verification for derived hardware-design elements
    5.
    发明授权
    Machine learning (ML)-based static verification for derived hardware-design elements 有权

    公开(公告)号：US11467851B1

    公开(公告)日：2022-10-11

    申请号：US17100625

    申请日：2020-11-20

    Applicant: Synopsys, Inc.

    Inventor： Kaushik De ,  Rajarshi Mukherjee ,  Paras Mal Jain ,  David L. Allen

    IPC: G06F9/445 ,  G06F30/33 ,  G06N20/00 ,  G06F30/20

    Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.

    RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS
    8.
    发明申请
    RANKING VERIFICATION RESULTS FOR ROOT CAUSE ANALYSIS 有权
    归因检验结果为原因分析

    公开(公告)号：US20140258954A1

    公开(公告)日：2014-09-11

    申请号：US13786599

    申请日：2013-03-06

    Applicant: SYNOPSYS, INC.

    Inventor： Kaushik De ,  Kevin M. Harer ,  Rajarshi Mukherjee ,  Mahantesh Narwade

    IPC: G06F17/50

    CPC classification number: G06F17/504

    Abstract: Verification-result ranking techniques for root cause analysis are disclosed using violation report analysis and violation weighting. Violation reports are unwieldy and result from a variety of design and process checks. The check coverage can overlap, causing a specific violation to trigger multiple reported violations. High turn around times for violation report analysis increase the risk that selective violation analysis will inadvertently suppress real design bugs. This reduces the odds that static checker reports alone will meet design sign-off criteria. Determining relationships among a plurality of violations for a design permits clustering violations into hot spots. Identification of primary and subsequent contributors to the plurality of violations is based on the relationships among violations. The hot spot with the highest weight is identified, and then subsequent violations are identified to maximize violation coverage. The result is greater efficiency of design violation identification and resolution.

    Abstract translation: 使用违规报告分析和违规加权披露了根本原因分析的验证结果排序技术。 违规报告是笨重的，并且是由各种设计和流程检查产生的。 检查覆盖可能重叠，导致特定违规触发多个报告的违规。 违规报告分析的高转时间增加了选择性违规分析将无意中压制真实设计错误的风险。 这减少了静态检查器报告单独符合设计签字标准的可能性。 确定设计的多个违规之间的关系允许将违规聚类到热点。 确定多个违规行为的主要和后续贡献者是基于违规行为之间的关系。 确定重量最大的热点，然后确定随后的违规行为，以最大限度地发挥违规覆盖率。 结果是设计违规识别和解决方案的效率更高。

    Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description
    10.
    发明申请
    Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description 审中-公开
    用于自动最小化电路描述的电路描述和系统的低功率验证方法

    公开(公告)号：US20160180012A1

    公开(公告)日：2016-06-23

    申请号：US14909018

    申请日：2014-07-23

    Applicant: SYNOPSYS, INC.

    Inventor： Dipti Ranjan Senapati ,  Kaushik De ,  Rajarshi Mukherjee ,  Shreedhar Ramachandra

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/5045 ,  G06F2217/78

    Abstract: A method for low power verification of a circuit description comprises minimizing a circuit description by creating a plurality of crossover trees, and evaluating each of the plurality of crossover trees to identify circuit description errors, in particular low power circuit description errors. The minimizing may comprise creating a plurality of crossover trees to represent circuit description, wherein each crossover tree has a unique set of selected ports and gates of the circuit description.

    Abstract translation: 用于电路描述的低功率验证的方法包括通过创建多个交叉树来最小化电路描述，并且评估多个交叉树中的每一个以识别电路描述错误，特别是低功率电路描述错误。 最小化可以包括创建多个交叉树以表示电路描述，其中每个交叉树具有电路描述的所选端口和门的唯一集合。

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