公开(公告)号：US09792394B2

公开(公告)日：2017-10-17

申请号：US15011546

申请日：2016-01-30

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Dipti Ranjan Senapati ,  Mahantesh D. Narwade ,  Namit K. Gupta ,  Rajarshi Mukherjee

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value. The enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction.

公开(公告)号：US20170053051A1

公开(公告)日：2017-02-23

申请号：US15011546

申请日：2016-01-30

Applicant: Synopsys, Inc.

Inventor： Kaushik De ,  Dipti Ranjan Senapati ,  Mahantesh D. Narwade ,  Namit K. Gupta ,  Rajarshi Mukherjee

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/62 ,  Y02P90/265

Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).

Abstract translation: 描述了用于检测电路设计中的设计问题的系统和技术。 可以合成电路设计的更高层次的抽象，以获得电路设计的较低级别抽象，以及较高级抽象中的信号与较低级别抽象中的信号之间的映射。 可以在电路设计中检测到设计问题，以响应于当使能信号被分配了阻塞值（确定了使能信号和相应的阻塞值）时，确定下级抽象中的信号中的可能的毛刺不被阻塞 通过分析上级抽象）。

公开(公告)号：US09990453B2

公开(公告)日：2018-06-05

申请号：US14673338

申请日：2015-03-30

Applicant: Synopsys, Inc.

Inventor： Namit K. Gupta ,  Jean-Marc A. Forey ,  Mahantesh D. Narwade ,  Horia A. Toma

IPC: G06F17/50 ,  G01R31/317

CPC classification number: G06F17/5031 ,  G01R31/317 ,  G06F17/5081 ,  G06F2217/14 ,  G06F2217/84

Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.

公开(公告)号：US20160292331A1

公开(公告)日：2016-10-06

申请号：US14673338

申请日：2015-03-30

Applicant: Synopsys, Inc.

Inventor： Namit K. Gupta ,  Jean-Marc A. Forey ,  Mahantesh D. Narwade ,  Horia A. Toma

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G01R31/317 ,  G06F17/5081 ,  G06F2217/14 ,  G06F2217/84

Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.

Abstract translation: 描述了与时域交叉（CDC）特定设计突变相关的模型硅行为和测量验证鲁棒性的方法和设备。 可以在电路设计中识别CDC信号路径。 接下来，可以识别与CDC信号路径相关联的同步电路。 设计突变可以添加到所识别的同步电路中。 然后可以在功能验证期间使用设计突变来测量电路验证测试套件的验证鲁棒性。